CS2200-OTP_09 Datasheet, PDF (16/24 Pages) Cirrus Logic – Fractional-N Frequency Synthesizer

5.7 Clock Output Stability Considerations
CS2200-OTP
5.7.1
Output Switching
The CS2200-OTP is designed such that re-configuration of the clock routing functions do not result in a
partial clock period on any of the active outputs (CLK_OUT and/or AUX_OUT). In particular, enabling or
disabling an output, changing the auxiliary output source between REF_CLK and CLK_OUT, and the au-
tomatic disabling of the output(s) during unlock will not cause a runt or partial clock period.
The following exceptions/limitations exist:
• Enabling/disabling AUX_OUT when AuxOutSrc[1:0] = 11 (unlock indicator).
• Switching AuxOutSrc[1:0] to or from 11 (unlock indicator)
(Transitions between AuxOutSrc[1:0] = [00,10] will not produce a glitch).
When any of these exceptions occur, a partial clock period on the output may result.
5.7.2
PLL Unlock Conditions
Certain changes to the clock inputs and mode pins can cause the PLL to lose lock which will affect the
presence of a clock signal on CLK_OUT. The following outlines which conditions cause the PLL to go un-
locked:
• Any change in the state of the M1 and M0 pins will cause the PLL to temporarily lose lock as the new
setting takes affect.
• Changes made to the state of the M2 when the M2Config[2:0] global parameter is set to 011, 100, 101,
or 110 can cause the PLL to temporarily lose lock as the new setting takes affect.
• Any discontinuities on the Timing Reference Clock, REF_CLK.
5.8 Required Power Up Sequencing for Programmed Devices
• Apply power. All input pins, except XTI/REF_CLK, should be held in a static logic hi or lo state until the
‘DC Power Supply’ specification in the “Recommended Operating Conditions” table on page 6 are met.
• Apply input clock.
• For CDK programmed devices, toggle the state of the M0, M1, or both pins at least 3 times to initialize
the device. This must be done after the power supply is stable and before normal operation is expected.
Note: This operation is not required for factory programmed devices.
• After the specified PLL lock time on page 7 has passed, the device will output the desired clock as con-
figured by the M0-M2 pins.
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