WM8232 Datasheet, PDF (15/141 Pages) Wolfson Microelectronics plc – 70MSPS 3-Channel AFE with Sensor Timing Generation and LVDS/CMOS Data Output

WM8232
Test Conditions
AVDD = LDOVDD = DBVDD = 3.3V, AGND = LDOGND = DBGND= 0V, T_A = 25C, MCLK= 35MHz unless otherwise stated.
PARAMETER
MCLK cycle period (see note 2)
MCLK high period (see note 2)
MCLK low period (see note 2)
MCLK rising edge to DLL tap 0
Aperture delay
(from RSMP falling edge)
Aperture delay
(from VSMP falling edge)
RSMP high period
VSMP high period
SYMBOL
t_PER
t_MCLKH
t_MCLKL
t_MCLKD
t_RSMPD
t_VSMPD
t_RSMPH
t_VSMPH
TEST CONDITIONS
MIN
28.6
0.4 * t_PER
0.4 * t_PER
5
5
RSMP falling edge to VSMP rising edge
t_RV
0.5
VSMP falling edge to RSMP rising edge
t_VR
0.5
Output data latency
LAT
LVDS 10-bit 5pair mode
(from 1^st falling edge of VSMP)
LVDS 10-bit 3pair mode,
CMOS 10-bit output mode
Other output modes
Notes:
TYP
0.5*t_PER
0.5*t_PER
18
5
5
18
16
17
MAX
200
0.6 * t_PER
0.6 * t_PER
UNITS
ns
ns
ns
ns
ns
ns
28 *
t_PER/60
ns
ns
ns
ns
clock
clock
clock
1. 1clock = t_PER (MCLK cycle period)
2. MCLK cycle period and MCLK high/low period are measured at 50% of the respective rising/falling edges
REGISTER
ADDRESS
R130 (82h)
RSMP rise
R131 (83h)
RSMP fall
R132 (84h)
VSMP rise
R133 (85h)
VSMP fall
BIT
LABEL
DEFAULT
DESCRIPTION
5:0
RSMP_RISE[5:0]
01_1100 RSMP rise edge (0 to 59)
5:0
RSMP_FALL[5:0]
10_0110 RSMP fall edge (0 to 59)
5:0
VSMP_RISE[5:0]
00_1000 VSMP rise edge (0 to 59)
5:0
VSMP_FALL[5:0]
10_1000 VSMP fall edge (0 to 59)
Rev 4.6
15