CS4352_07 Datasheet, PDF (15/20 Pages) Cirrus Logic – 192 kHz Stereo DAC with 2 Vrms Line Out

4.9 Initialization and Power-Down Sequence Diagram
USER: Apply Power
Power-Down State
VQ and outputs low
VQ and outputs
ramp down
USER: Apply MCLK, SCLK, LRCK,
and release RST
VQ and outputs ramp up
CS4352
USER: Apply RST
Wait State
USER: Remove
LRCK or MCLK
USER: Apply MCLK, SCLK, and LRCK
MCLK/LRCK Ratio Detection
USER: change
MCLK/LRCK ratio
Analog Output
is Generated
DS684F2
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