CS4352_07 Datasheet, PDF (12/20 Pages) Cirrus Logic – 192 kHz Stereo DAC with 2 Vrms Line Out

CS4352
4.3 Digital Interface Format
The device will accept audio samples in 1 of 4 digital interface formats, as illustrated in Table 5.
The desired format is selected via the DIF1 and DIF0 pins. For an illustration of the required relationship
between the LRCK, SCLK and SDIN, see Figures 3-5. For all formats, SDIN is valid on the rising edge of
SCLK. Also, SCLK must have at least 32 cycles per LRCK period in format 2 and 48 cycles per LRCK period
in format 3.
For more information about serial audio formats, refer to Cirrus Logic Application Note AN282: The 2-Chan-
nel Serial Audio Interface: A Tutorial, available at www.cirrus.com.
DIF1
0
0
1
1
DIF0
DESCRIPTION
0 I²S, up to 24-bit Data
1 Right-Justified, 24-bit Data
0 Left-Justified, up to 24-bit Data
1 Right-Justified, 16-bit Data
FORMAT
0
1
2
3
FIGURE
3
4
5
4
Table 5. Digital Interface Format
LRCK
SCLK
SDIN
Left Channel
Right Channel
MSB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4
+5 +4 +3 +2 +1 LSB
Figure 3. I²S, up to 24-Bit Data
LRCK
SCLK
SDIN MSB
Left Channel
R ight Cha nnel
MSB +1 +2 +3 +4 +5
-7 -6 -5 -4 -3 -2 -1 LSB
MSB +1 +2 +3 +4 +5
-7 -6 -5 -4 -3 -2 -1 LSB
Figure 4. Right-Justified Data
LRCK
SCLK
SDIN
Left Channel
Right Channel
MSB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4
+5 +4 +3 +2 +1 LSB
Figure 5. Left-Justified up to 24-Bit Data
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DS684F2