CS4334_04 Datasheet, PDF (15/25 Pages) Cirrus Logic – 8-Pin, 24-Bit, 96 kHz Stereo D/A Converter

CS4334/5/8/9
LRCK
SCLK
SDATA
Left Channel
MSB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LSB
Right Channel
MSB -1 -2 -3 -4 +5 +4 +3 +2 +1 LSB
Internal SCLK Mode
I²S, 16-Bit data and INT SCLK = 32 Fs if
MCLK/LRCK = 512, 256 or 128
I²S, Up to 24-Bit data and INT SCLK = 48 Fs if
MCLK/LRCK = 384 or 192
External SCLK Mode
I²S, up to 24-Bit Data
Data Valid on Rising Edge of SCLK
Figure 10. CS4334 Data Format (I²S)
LRCK
SCLK
SDATA
Left Channel
MSB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LSB
Right Channel
MSB -1 -2 -3 -4 +5 +4 +3 +2 +1 LSB
Internal SCLK Mode
Left Justified, up to 24-Bit Data
INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128
INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
External SCLK Mode
Left Justified, up to 24-Bit Data
Data Valid on Rising Edge of SCLK
Figure 11. CS4335 Data Format
LRCK
SCLK
Left Channel
Right Channel
SDATA
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 clocks
Internal SCLK Mode
Right Justified, 16-Bit Data
INT SCLK = 32 Fs if MCLK/LRCK = 512, 256 or 128
INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
External SCLK Mode
Right Justified, 16-Bit Data
Data Valid on Rising Edge of SCLK
SCLK Must Have at Least 32 Cycles per LRCK Period
Figure 12. CS4338 Data Format
DS248F3
15