CS22230 Datasheet, PDF (13/29 Pages) Cirrus Logic – WIRELESS PCI/USB CONTROLLER

RXCLK
MDRDY
RXD
DACAVCC
DACAGND
Input
This is an input from Base Band Processor. It is used to clock in received
data from Base Band Processor.
Input
Receive data ready is an input signal from the baseband processor,
indicating a data packet is ready to be transferred to the MAC. The signal
returns to inactive state when there is no more receiver data or when the
link has been interrupted. This signal is sampled on the falling edge of
RXCLK (in 3824 mode), and sampled at rising edge of RXCLK (in 3860B
mode).
Input
Receive data is an input from the baseband processor transferring
demodulated header information and data in a serial format. The data is
frame aligned with MD_RDY. This signal is sampled on the falling edge of
RXCLK (in 3824 mode), and sampled at rising edge of RXCLK (in 3860B
mode).
Analog power for DAC. 3.3V input.
Input
Analog ground for DAC.
Input
PLL and Clock Interface
There are three clock pins and five PLL power pins. There are a t of 8 signals in this interface.
XTAL_CLKIN
Input
44 MHz Reference clock input/crystal clock input for Mini PCI and 48 MHz
for USB.
XTALOUT
Reference crystal clock output.
Output
XTRACLK
Input
Second clock input to clock module. This input allows independent control
for mem_clk and ctl_clk. The usage of this clock input is determined by the
clk module configuration, which is determined by the three strapping input
pin values.
CS22230 Mini PCI / USB Wireless Controller
13 of 29
www.cirrus.com
DS558PP1 Rev. 1.0