WM8325 Datasheet, PDF (110/254 Pages) Wolfson Microelectronics plc – Processor Power Management Subsystem

WM8325
GPn_FN
8h
9h
Ah
Bh
Ch
Dh
Eh
Fh
GPIO INPUT
FUNCTION
Hardware DVS
control 1
Hardware DVS
control 2
Hardware
Enable 1
Hardware
Enable 2
Hardware
Control input 1
Hardware
Control input 2
Hardware
Control input 1
Hardware
Control input 2
DESCRIPTION
Control input for selecting the DVS output
voltage in one or more DC-DC Converters.
See Section 15.6.
Control input for selecting the DVS output
voltage in one or more DC-DC Converters.
See Section 15.6.
Control input for enabling one or more DC-DC
Converters and LDO Regulators.
See Section 15.
Control input for enabling one or more DC-DC
Converters and LDO Regulators.
See Section 15.
Control input for selecting the operating mode
and/or output voltage of one or more DC-DC
Converters and LDO Regulators.
See Section 15.
Control input for selecting the operating mode
and/or output voltage of one or more DC-DC
Converters and LDO Regulators.
See Section 15.
Control input for selecting the operating mode
and/or output voltage of one or more DC-DC
Converters and LDO Regulators.
See Section 15.
Control input for selecting the operating mode
and/or output voltage of one or more DC-DC
Converters and LDO Regulators.
See Section 15.
Table 52 List of GPIO Input Functions
Production Data
DE-BOUNCE
TIME
None
None
32s to 64s
32s to 64s
32s to 64s
32s to 64s
32ms to 64ms
32ms to 64ms
Further details of the GPIO input de-bounce time are noted in Section 21.3.
GPn_FN
0h
1h
2h
3h
4h
8h
9h
GPIO OUTPUT
FUNCTION
GPIO
Oscillator clock
ON state
SLEEP state
Power State
Change
DC-DC1 DVS
Done
DC-DC2 DVS
Done
DESCRIPTION
GPIO output. Logic level is set by writing to the GPn_LVL
register bits. See Section 21.3.
32.768kHz clock output. See Section 13.
Logic output indicating that the WM8325 is in the ON state. See
Section 11.5.
Logic output indicating that the WM8325 is in the SLEEP state.
See Section 11.5.
Logic output asserted whenever a Power On Reset, or an ON,
OFF, SLEEP or WAKE transition has completed.
Under default polarity (GPn_POL=1), the logic level is the same
as the PS_INT interrupt status flag. Note that, if any of the
associated Secondary interrupts is masked, then the respective
event will not affect the Power State Change GPIO output.
See Section 11.2 and Section 11.4.
Logic output indicating that DC-DC1 buck converter DVS slew
has been completed. This signal is temporarily de-asserted
during voltage transitions (including non-DVS transitions). See
Section 15.6.
Logic output indicating that DC-DC1 buck converter DVS slew
has been completed. This signal is temporarily de-asserted
during voltage transitions (including non-DVS transitions). See
Section 15.6.
w
PD, February 2012, Rev 4.0
110