CS42418_05 Datasheet, PDF (11/73 Pages) Cirrus Logic – 110 dB, 192 kHz 8-Ch Codec with PLL

CS42418
SWITCHING CHARACTERISTICS
(For CQZ, T_A = -10 to +70° C; For DQZ, T_A = -40 to +85° C;
VA = 5 V, VD =VLC= 3.3 V, VLS = 1.8 V to 5.25 V; Inputs: Logic 0 = DGND, Logic 1 = VLS, C_L = 30 pF)
Parameters
Symbol
Min
Typ
Max
Units
RST Pin Low Pulse Width
(Note 12)
PLL Clock Recovery Sample Rate Range
RMCK Output Jitter
(Note 14)
RMCK Output Duty Cycle
(Note 15)
OMCK Frequency
(Note 13)
OMCK Duty Cycle
(Note 13)
DAC_SCLK, ADC_SCLK Duty Cycle
DAC_LRCK, ADC_LRCK Duty Cycle
Master Mode
RMCK to DAC_SCLK, ADC_SCLK active edge delay
t_smd
RMCK to DAC_LRCK, ADC_LRCK delay
t_lmd
Slave Mode
1
30
-
45
1.024
40
45
45
0
0
-
-
ms
-
200
kHz
200
-
ps RMS
50
55
%
-
25.600
MHz
50
60
%
50
55
%
50
55
%
-
15
ns
-
15
ns
DAC_SCLK, ADC_SCLK Falling Edge to ADC_SDOUT,
ADC_SDOUT Output Valid
t_dpd
DAC_LRCK, ADC_LRCK Edge to MSB Valid
t_lrpd
DAC_SDIN Setup Time Before DAC_SCLK Rising Edge
t_ds
10
DAC_SDIN Hold Time After DAC_SCLK Rising Edge
t_dh
30
DAC_SCLK, ADC_SCLK High Time
t_sckh
20
DAC_SCLK, ADC_SCLK Low Time
t_sckl
20
DAC_SCLK, ADC_SCLK falling to DAC_LRCK, SAI_LRCK
Edge
t_lrck
-25
-
(Note 16)
ns
-
26.5
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
+25
ns
Notes:
12. After powering-up the CS42418, RST should be held low after the power supplies and clocks are set-
tled.
13. See Table 1 on page 24 for suggested OMCK frequencies
14. Limit the loading on RMCK to 1 CMOS load if operating above 24.576 MHz.
15. Not valid when RMCK_DIV in “Clock Control (address 06h)” on page 48 is set to Multiply by 2.
16. 76.5 ns for Single-Speed and Double-Speed modes, 23 ns for Quad-Speed Mode.
DAC_SCLK
ADC_SCLK
(output)
DAC_LRCK
ADC_LRCK
(output)
RMCK
t _smd
t _lmd
DAC_LRCK
ADC_LRCK
(input)
DAC_SCLK
ADC_SCLK
(input)
t _lrckd
t _lrcks
t _sckh
tsckl
DAC_SDINx
ADC_SDOUT
t_{lrpd tds}
tdh
MSB
tdpd
MSB-1
Figure 1. Serial Audio Port Master Mode Timing
DS603F1
Figure 2. Serial Audio Port Slave Mode Timing
11