CS1501 Datasheet, PDF (11/16 Pages) Cirrus Logic – Digital Power Factor Correction Control IC

CS1501
Resistor R_IFB sets the feedback current and is calculated as
follows:
R_IFB = ^V-----l-ⁱ--ⁿ--^k-I--_r-^–-_e---_f-V----^D----^D-- = ^{4----0--1-0---2-V--9---–}-m----V-A---^D----^D--
[Eq.4]
By using digital loop compensation, the voltage feedback
signal does not require an external compensation network.
A current proportional to the AC input voltage is supplied to the
IC on pin IAC and is used by the PFC control algorithm.
V _rect
R1
I_AC
R_IAC
V DD
R2
8
CS1501
IA C
3
15 k
24k
Iref
ADC
Figure 18. IAC Input Pin Model
Resistor R_IAC sets the I_AC current and is derived as follows:
R_IAC = R_IFB
[Eq.5]
For optimal performance, resistors R_IAC & R_IFB should use 1%
tolerance or better resistors for best V_link voltage accuracy.
5.7 Valley Switching
The zero-current detection (ZCD) pin is monitored for
demagnetization in the auxiliary winding of the boost inductor
(L_B). The ZCD circuit is designed to detect the V_Aux
valley/zero crossings by sensing the voltage transformed onto
the auxiliary winding of L_B.
L_B
N:1
V_link
D2
FE T Drain
I_Aux
R3
I_{Z CD}
+
V_{Aux R4}
-
CS1501
5
ZC D
Cp
+
- _{Vth( Z CD)}
D e ma g
Comparator
ZCD_below_z ero
Figure 19. ZCD Input Pin Model
The objective of zero-voltage switching is to initiate each
MOSFET switching cycle when its drain-source voltage is at
the lowest possible voltage potential, thus reducing switching
losses. CS1501 uses an auxiliary winding on the PFC boost
inductor to implement zero-voltage switching.
Zero Crossing
Detection
ZCD
ZCD_below _zero
GD ‘ON’
Figure 20. Zero-voltage Switch
During each switching cycle, when the boost diode current
reaches zero, the boost MOSFET drain-source voltage begins
oscillating at the resonant frequency of the boost inductor and
MOSFET parasitic output capacitance. The ZCD_below_zero
signal transitions from high to low just prior to a local minimum
of the MOSFET drain-source voltage oscillation. The
zero-crossing detect circuit ensures that a ZCD_below_zero
pulse will only be generated when the comparator output is
continuously high for a nominal time period (t_ZCB) of 200ns.
Therefore, any negative edges on the comparator's output
due to spurious glitches will not cause a pulse to be
generated. Due to the CS1501’s variable-frequency control,
the MOSFET switching cycle will not always be initiated at the
first resonant valley.
The external circuitry should be designed so that the current
(I_ZCD) at the ZCD pin is approximately 1.0 mA. The table
below depicts approximate values for R3 and R4 for a range
of boost-to-auxiliary inductor turns ratio, N.
N
~R3
~R4
9
46 k
1.75 k
10
42 k
1.75 k
11
37.5 k
1.75 k
12
35.5 k
1.75 k
13
32 k
1.75 k
14
29.5 k
1.75 k
15
27.5 k
1.75 k
Table 1. Aux Inductor Turns Ratio vs. R3 and R4
Resistors R3 and R4 were calculated using V_link = 400V and
C_p = 10pF.
Equation 6 is used to calculate the cut-off frequency defined
by the RC circuit at the ZCD pin.
where:
f_c
C_p
f_c = 1  2R3  R4C_p
[Eq.6]
The cut-off frequency, f_c, needs to be 10x the ringing
frequency
Capacitance at the ZCD pin
DS927PP6
11