CS1501 Datasheet, PDF(10/16 Page) Cirrus Logic – Digital Power Factor Correction Control IC

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CS1501 Datasheet, PDF (10/16 Pages) Cirrus Logic – Digital Power Factor Correction Control IC

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CS1501

5.3 Burst Mode

Burst mode is utilized to improve system efficiency when the

system output power (Po) is <5% of nominal. Burst mode is

implemented by intermittently disabling the PFC over a full

half-line period under light-load conditions, as shown in

Figure 15.

[W]

Burst Threshold

Burst Mode

Active

t [ms]

Vin

[V]

Vin

PFC

Disable

FET

Vgs

Solving Equation 2 for the PFC boost inductor, LB, gives the

following equation:

LB = ï¡ ï´ ï¨ ï´ ï¨90Vï©2 ï´ 2-----ï´-4----07---00----Vk----H-â---z--ï¨--9-ï´--0---P-V-o-----ï´-ï´-----4---20---0ï©----V--

[Eq.3]

If a value of the boost inductor other than that obtained from

Equation 3 above is used, the total output power capability as

well as the minimum input voltage threshold will differ

according to Equation 2. Note that if the input voltage drops

below 90Vrms and the inductance value is <LB, the link

voltage Vlink will drop below 400V and fall out of regulation.

L < LB ï¯ï¡

L = LB

L > LBï¯ï¡

t [ms]

Figure 15. Burst Mode

5.4 Output Power and PFC Boost Inductor

In normal operating mode, the nominal output power is

estimated by the following equation.

Po = ï¡ ï´ ï¨ ï´ ï¨Vinï¨minï©ï©2 ï´ -V--2--l-i--nï´--k---f-âm-----aï¨--V-x---i-ï´-n---ï¨-L-m---B-i-n--ï´-ï©---ï´V-----l-i-n--2-k---ï©-

[Eq.1]

where:

rated output power of the system

ï¨

efficiency of the boost converter (estimated as 100%

by the PFC algorithm)

Vin(min) minimum RMS line voltage is 90V, measured after

the rectifier and EMI filter

Vlink nominal PFC output voltage (must be 400V)

fmax maximum switching frequency is 70kHz

boost inductor specified by rated power requirement

ï¡<1 margin factor to guarantee rated output power (Po)

against boost inductor tolerances.

Equation 1 is provided for explanation purposes only. Using

substituted required design values for Vlink and fmax gives the

following equation:

Po = ï¡ ï´ ï¨ ï´ ï¨90Vï©2 ï´ 2-----ï´-4---0-7---00---V-k----H-â---z-ï¨---9-ï´--0---L-V---B--ï´--ï´----4---2-0---0ï©----V--

[Eq.2]

Changing the value for the Vlink voltage is not recommended.

265

VAC(rms)

Figure 16. Relative Effects of Varying Boost Inductance

5.5 PFC Output Capacitor

The value of the PFC output capacitor should be chosen

based upon voltage ripple and hold-up requirements. To

ensure system stability with the digital controller, the

recommended value of the capacitor is within the range of

0.5ïF/watt to 2.0ïF/watt with a Vlink voltage of 400V.

5.6 Output IFB Sense & Input IAC Sense

A current proportional to the PFC output voltage, Vlink, is

supplied to the IC on pin IFB and is used as a feedback control

signal. This current is compared against an internal

fixed-value reference current.

The ADC is used to measure the magnitude of the IIFB current

through resistor RIFB. The magnitude of the IIFB current is then

compared to an internal reference current (Iref) of 129ïA.

V link

IFB

RIFB

VDD

CS1501

IFB

15k

24 k

Iref

ADC

Figure 17. IFB Input Pin Model

DS927PP6

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