CS4124 Datasheet, PDF (3/6 Pages) Cherry Semiconductor Corporation – High Side PWM FET Controller

Electrical Characteristics: 4V ≤ V_CC ≤ 26V, -40˚C < T_A = 125°C, (unless otherwise specified)
PARAMETER
TEST CONDITIONS
s External Drive (OUTPUT): continued
Voltage to Duty Cycle
Conversion
4V ≤ V_CC < 7V
V_CC = 13V, CTL = 1V
V_CC = 13V, CTL = 2V
7V ≤ V_CC ≤ 18V
V_CC = 13V, CTL = 30% V_REG
V_CC = 13V, CTL = 55.8% V_REG
18V < V_CC ≤ 26V
V_CC = 13V, CTL = 1. 5V
V_CC = 13V, CTL = 3. 5V
Output Rise Time
4V ≤ V_CC ≤ 26V
R_GATE = 6Ω, C_GATE = 5nF
Output Fall Time
4V ≤ V_CC ≤ 26V
R_GATE = 6Ω, C_GATE = 5nF
Output Sink Current
4V ≤ V_CC < 7V
R_GATE = 6Ω, C_GATE = 5nF
7V ≤ V_CC ≤ 26V
R_GATE = 6Ω, C_GATE = 5nF
Output Source Current
4V ≤ V_CC < 7V
R_GATE = 6Ω, C_GATE = 5nF
7V ≤ V_CC ≤ 26V
R_GATE = 6Ω, C_GATE = 5nF
Output High Voltage
I_OUT = 1mA
Output Low Voltage
I_OUT = -1mA
MIN
TYP
MAX
65
75
100
28.3
36.3
56.0
64.0
11.8
21.8
34.2
44.2
.25
1
.30
1
150
300
150
300
V_BOOST - 1.7
1.3
s Charge Pump (DRV)
Boost Voltage
PACKAGE LEAD #
16 Lead PDIP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
V_CC + 6.4
Package Lead Description
LEAD SYMBOL
FUNCTION
OUTPUT
BOOST
FLT
R_OSC
C_OSC
CTL
PGnd
V_CC
V_REG
SNI
PMP
I_SENSE-
I_SENSE+
I_ADJ
INH
Gnd
MOSFET gate drive
Boost voltage
Fault time out capacitor
Oscillator resistor
Oscillator capacitor
Pulse width control input
Power ground for on chip clamp
Positive power supply input
5V linear regulator
Sense inductor current
Collector of boost power transistor
Current sense minus
Current sense plus
Current limit adjust
Output Inhibit
Ground
1197
UNIT
%
%
%
%
%
%
µs
µs
mA
mA
mA
mA
V
V
V