CS5166 Datasheet, PDF (14/22 Pages) Cherry Semiconductor Corporation – 5-Bit Synchronous CPU Controller with Power-Good and Current Limit

Application Information: continued
3) Thermal Considerations
Due to I² × R power losses the surface temperature of
the droop resistor will increase causing the resistance
to increase. Also, the ambient temperature variation
will contribute to the increase of the resistance,
according to the formula:
where:
R = R₂₀ [1+ α₂₀(Τ−20)]
R₂₀ = resistance at 20˚C
α = ^0.00393
˚C
T= operating temperature
R = desired droop resistor value
For temperature T = 50˚C,
the % R change = 12%
Droop Resistor Tolerance
Tolerance due to sheet resistivity variation
16%
Tolerance due to L/W error
1%
Tolerance due to temperature variation
12%
Total tolerance for droop resistor
29%
In order to determine the droop resistor value the nominal
voltage drop across it at full load has to be calculated. This
voltage drop has to be such that the output voltage full
load is above the minimum DC tolerance spec.
V_DROOP(TYP) =
[V_DAC(MIN)-V_DC(MIN)]
1+R_{DROOP(TOLERANCE)}
Example: for a 300MHz Pentium^®II, the DC accuracy spec
is 2.74 < V_CC(CORE) < 2.9V, and the AC accuracy spec is
2.67V < V_CC(CORE) <2.93V. The CS5166 DAC output volt-
age is +2.796V < V_DAC < +2.853V. In order not to exceed
the DC accuracy spec, the voltage drop developed across
the resistor must be calculated as follows:
V_DROOP(TYP) =
[V_DAC(MIN)-V_{DC PENTIUM®II(MIN)}]
1+R_{DROOP(TOLERANCE)}
2.796V-2.74V
=
= 43mV
1.3
With the CS5166 DAC accuracy being 1%, the internal
error amplifier’s reference voltage is trimmed so that the
output voltage will be 25mV high at no load. With no load,
there is no DC drop across the resistor, producing an out-
put voltage tracking the error amplifier output voltage,
including the offset. When the full load current is deliv-
ered, a drop of -43mV is developed across the resistor.
Therefore, the regulator output is pre-positioned at 25mV
above the nominal output voltage before a load turn-on.
The total voltage drop due to a load step is ∆V-25mV and
the deviation from the nominal output voltage is 25mV
smaller than it would be if there was no droop resistor.
Similarly at full load the regulator output is pre-positioned
at 18mV below the nominal voltage before a load turn-off.
the total voltage increase due to a load turn-off is ∆V-18mV
and the deviation from the nominal output voltage is
18mV smaller than it would be if there was no droop resis-
tor. This is because the output capacitors are pre-charged
to value that is either 25mV above the nominal output
voltage before a load turn-on or, 18mV below the nominal
output voltage before a load turn-off (see Figure 8).
Obviously, the larger the voltage drop across the droop
resistor (the larger the resistance), the worse the DC and
load regulation, but the better the AC transient response.
Current Limit Setpoint Calculations
The following is the design equation used to set the cur-
rent limit trip point by determining the value of the
embedded PCB trace used as a current sensing element.
The current limit setpoint has to be higher than the normal
full load current. Attention has to be paid to the current
V_IN
Q1
L
Q2
R_DROOP
IFB
RFB
V_OUT
C_OUT
R_ISENSE
ISENSE
CS5166
V_FB
I_SENSE
Current Limit Comparator
+
-
V_TH
I_SENSE
Figure 22: Circuit used to determine the voltage across the droop resistor that will trip the internal current sense comparator.
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