CM8500A Datasheet, PDF (8/13 Pages) List of Unclassifed Manufacturers – 3A BUS TERMINATOR

CM8500ATEVAL PCB LAYOUT
CM8500A
3A BUS TERMINATOR
Figure 4. CM8500AEVAL PCB Layout
SSTL-2 SPECIFICATIONS
SYMBOL
PARAMETER
V_DD
V_DDQ
V_REF
Device Supply Voltage
Output Supply Voltage
Input Reference Voltage
V_TT
Termination Voltage
INPUT DC LOGIC LEVELS
V_IH (DC)
DC Input Logic High
V_IL (DC)
DC Input Logic Low
INPUT AC LOGIC LEVELS
V_IH (AC)
AC Input Logic High
V_IL (AC)
AC Input Logic Low
OUTPUT DC CURRENT DRIVE
I_OH (DC)
I_OL (DC)
Output Minimum Source DC Current
Output Minimum Sink DC Current
MIN
V_DDQ
2.3
1.15
V_REF - 0.04
V_REF + 0.18
- 0.3
V_REF + 0.35
- 15.2
15.2
TYP
2.5
1.25
V_REF
Notes:
VREF and VTT must track variations in VDDQ
Peak-to-peak AC noise on V_REF may not exceed ±2% V_REF (DC)
V_TT of transmitting device must track V_REF of receiving device
Table 1. Key Specifications for SSTL_2
MAX
N/A
2.7
1.35
V_REF + 0.04
V_DDQ + 0.3
V_REF - 0.18
V_REF - 0.35
UNITS
V
V
V
V
V
V
V
V
mA
mA
2008/01/16
Champion Microelectronic Corporation
Page 8