CEP10N6 Datasheet, PDF (5/5 Pages) Chino-Excel Technology – N-Channel Logic Level Enhancement Mode Field Effect Transistor

CEP10N6/CEB10N6
15
VDS=480V
12 ID=5A
4
9
100_ij
s
10¹
6
3
0
0
20
40
60
80
Qg, Total Gate Charge (nC)
Figure 9. Gate Charge
10⁰
TC=25 C
Tj=150 C
-1 ^{Single Pulse}
10
10⁰
10¹
10²
10³
VDS, Drain-Source Voltage (V)
Figure 10. Maximum Safe
Operating Area
VDD
RL
VIN
D
VOUT
VGS
RGEN _G
S
td(on)
VOUT
t on
tr
td(off)
90%
10% INVERTED
toff
tf
90%
10%
VIN
10%
50%
90%
50%
PULSE WIDTH
Figure 11. Switching Test Circuit
Figure 12. Switching Waveforms
10⁰
D=0.5
0.2
10^{-1 0.1}
0.05
0.02
0.01
Single Pulse
10^-2
10^-5
10^-4
PDM
t1
t2
10^-3
10^-2
10^-1
1. RįJC (t)=r (t) * RįJC
2. RįJC=See Datasheet
3. TJM-TC = P* RįJC (t)
4. Duty Cycle, D=t1/t2
10⁰
10¹
Square Wave Pulse Duration (sec)
Figure 13. Normalized Thermal Transient Impedance Curve
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