CEF07N8 Datasheet, PDF (4/5 Pages) Chino-Excel Technology – N-Channel Logic Level Enhancement Mode Field Effect Transistor

CEF07N8
1800
Ciss
1500
1200
900
2.2
ID=4
VGS=10V
1.9
1.6
1.3
600
1.0
300
Coss
0.7
64
Crss
0
0.4
0
5
10
15
20 25
-100 -50 0 50 100 150 200
VDS, Drain-to Source Voltage (V)
Figure 3. Capacitance
TJ, Junction Temperature( C)
Figure 4. On-Resistance Variation with
Temperature
1.30
1.15
1.20
VDS=VGS
ID=250ijA
1.10 ^ID=250ijA
1.10
1.05
1.0
0.90
0.80
0.70
0.60
-50 -25 0
25 50
75 100 125 150
1.00
0.95
0.90
0.85
-50 -25 0 25 50 75 100 125 150
Tj, Junction Temperature ( C)
Figure 5. Gate Threshold Variation
with Temperature
4
VDS=50V
3
Tj, Junction Temperature ( C)
Figure 6. Breakdown Voltage Variation
with Temperature
20
10 ^VGS=0V
2
1
0
0
1
2
3
4
IDS, Drain-Source Current (A)
Figure 7. Transconductance Variation
with Drain Current
6-140
1
0.1
0.4
0.6
0.8
1.0
1.2
VSD, Body Diode Forward Voltage (V)
Figure 8. Body Diode Forward Voltage
Variation with Source Current