24LC08 Datasheet, PDF (7/23 Pages) Ceramate Technical – 8K-Bit Serial EEPROM

24LC08
8K-Bit Serial EEPROM
Master
SCL Line
Data from
Transmitter
ACK from
Receiver
Bit 1
Bit 9
ACK
Figure 3-8. Acknowledge Response From Receiver
• Slave Address: After the master initiates a Start condition, it must output the address of the device to be
accessed. The most significant four bits of the slave address are called the “device identifier”. The identifier
for the 24LC08 is “1010B”. The next three bits comprise the addr ess of a specific device. The device
address is defined by the state of the A0, A1 and A2 pins. Using this addressing scheme, you can cascade
up to two 24LC08 on the bus (see Table 3-2 below). The b1, b2 for 24LC08 are used by the master
to select which of the blocks of internal memory (1 block = 256 words) are to be accessed. The bits are in
effect the most significant bits of the word address.
• Read/Write: The final (eighth) bit of the slave address defines the type of operation to be performed. If the
R/W bit is “1”, a read operation is executed. If it is “0”, a write operation is executed.
Device
24LC08
Table 3-2. Slave Device Addressing
Device Identifier
b7 b6 b5 b4
1010
Device Address
b3
b2
b1
A2
B1
B0
R/W Bit
b0
R/W
NOTE: The A2, B1, B0 correspond to the MSB of the memory array address word.
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN
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Rev 1.1 Nov.18, 2002