CMLDM8120 Datasheet, PDF (2/2 Pages) Central Semiconductor Corp – SURFACE MOUNT P-CHANNEL ENHANCEMENT-MODE SILICON MOSFET

CMLDM8120
CMLDM8120G*
SURFACE MOUNT
P-CHANNEL
ENHANCEMENT-MODE
SILICON MOSFET
ELECTRICAL CHARACTERISTICS - Continued: (TA=25°C unless otherwise noted)
SYMBOL TEST CONDITIONS
MIN
TYP
MAX
gFS
VDS=10V, ID=0.81A
2.0
Crss
VDS=16V, VGS=0, f=1.0MHz
80
Ciss
VDS=16V, VGS=0, f=1.0MHz
200
Coss
VDS=16V, VGS=0, f=1.0MHz
60
ton
VDD=10V, VGS=4.5V, ID=0.95A, RG=6Ω
20
toff
VDD=10V, VGS=4.5V, ID=0.95A, RG=6Ω
25
SOT-563 CASE - MECHANICAL OUTLINE
UNITS
S
pF
pF
pF
ns
ns
PIN CONFIGURATION
w w w. c e n t r a l s e m i . c o m
LEAD CODE:
1) Drain
2) Drain
3) Gate
4) Source
5) Drain
6) Drain
MARKING CODES:
CMLDM8120: C81
CMLDM8120G*: C8G
* Device is Halogen Free by design
R3 (18-January 2010)