CMLDM7002A_15 Datasheet, PDF (2/4 Pages) Central Semiconductor Corp – SURFACE MOUNT SILICON DUAL N-CHANNEL ENHANCEMENT-MODE MOSFETS

CMLDM7002A
CMLDM7002AG*
CMLDM7002AJ
SURFACE MOUNT SILICON
DUAL N-CHANNEL
ENHANCEMENT-MODE
MOSFETS
ELECTRICAL CHARACTERISTICS PER TRANSISTOR - Continued: (TA=25°C unless otherwise noted)
SYMBOL TEST CONDITIONS
TYP
MAX
UNITS
Crss
VDS=25V, VGS=0, f=1.0MHz
5.0
pF
Ciss
VDS=25V, VGS=0, f=1.0MHz
50
pF
Coss
VDS=25V, VGS=0, f=1.0MHz
25
pF
Qg(tot)
VDS=30V, VGS=4.5V, ID=100mA
0.592
nC
Qgs
VDS=30V, VGS=4.5V, ID=100mA
0.196
nC
Qgd
VDS=30V, VGS=4.5V, ID=100mA
0.148
nC
ton, toff
VDD=30V, VGS=10V, ID=200mA
RG=25Ω, RL=150Ω
20
ns
SOT-563 CASE - MECHANICAL OUTLINE
PIN CONFIGURATIONS
CMLDM7002A (USA Pinout)
CMLDM7002AG*
LEAD CODE:
1) Gate Q1
2) Source Q1
3) Drain Q2
4) Gate Q2
5) Source Q2
6) Drain Q1
CMLDM7002AJ (Japanese Pinout)
LEAD CODE:
1) Source Q1
2) Gate Q1
3) Drain Q2
4) Source Q2
5) Gate Q2
6) Drain Q1
MARKING CODES:
CMLDM7002A: L02
CMLDM7002AG*: C2G
* Device is Halogen Free by design
w w w. c e n t r a l s e m i . c o m
MARKING CODE: 02J
R8 (8-June 2015)