CMLDM5757_13 Datasheet, PDF (2/3 Pages) Central Semiconductor Corp – SURFACE MOUNT SILICON DUAL P-CHANNEL ENHANCEMENT-MODE MOSFET

CMLDM5757
SURFACE MOUNT SILICON
DUAL P-CHANNEL
ENHANCEMENT-MODE
MOSFET
ELECTRICAL CHARACTERISTICS PER TRANSISTOR - Continued: (TA=25°C)
SYMBOL TEST CONDITIONS
TYP
MAX
Qg(tot)
VDS=10V, VGS=4.5V, ID=200mA
1.2
Qgs
VDS=10V, VGS=4.5V, ID=200mA
0.24
Qgd
VDS=10V, VGS=4.5V, ID=200mA
0.36
ton
VDD=10V, VGS=4.5V, ID=215mA, RG=10Ω
38
toff
VDD=10V, VGS=4.5V, ID=215mA, RG=10Ω
48
SOT-563 CASE - MECHANICAL OUTLINE
UNITS
nC
nC
nC
ns
ns
PIN CONFIGURATION
LEAD CODE:
1) Source Q1
2) Gate Q1
3) Drain Q2
4) Source Q2
5) Gate Q2
6) Drain Q1
MARKING CODE: 77C
w w w. c e n t r a l s e m i . c o m
R2 (5-June 2013)