CP210 Datasheet, PDF (1/3 Pages) Central Semiconductor Corp – Small Signal Transistors N - Channel Silicon Amplifer J FET Chip

PROCESS CP210
Small Signal Transistors
N - Channel Silicon Amplifer J FET Chip
Central^TM
Semiconductor Corp.
PROCESS DETAILS
Process
Die Size
Die Thickness
Drain Bonding Pad Area
Source Bonding Pad Area
Gate Bonding Pad Area
Top Side Metalization
Back Side Metalization
GEOMETRY
EPITAXIAL PLANAR
15 x 15 MILS
8.0 MILS
3.2 X 4.0 MILS
3.2 X 4.0 MILS
3.2 X 4.0 MILS
Al - 30,000Å
Au - 6,000Å
GROSS DIE PER 4 INCH WAFER
53,730
PRINCIPAL DEVICE TYPES
2N4416A
CMPF4416A
BACKSIDE GATE
145 Adams Avenue
Hauppauge, NY 11788 USA
Tel: [phone]
Fax: [phone]
www.centralsemi.com
R3 (9 -September 2003)