CAT28LV256_04 Datasheet, PDF (9/12 Pages) Catalyst Semiconductor – 256K-Bit CMOS PARALLEL E2PROM

CAT28LV256
HARDWARE DATA PROTECTION
The following hardware data protection features are
incorporated into the CAT28LV256.
(1) V_CC sense provides write protection when V_CC falls
below 2.0V min.
(2) A power on delay mechanism, tINIT (see AC charac-
teristics), provides a 5 to 10 ms delay before a write
sequence, after VCC has reached 2.4V min.
(3) Write inhibit is activated by holding any one of OE
low, CE high, or WE high.
(4) Noise pulses of less than 20 ns on the WE or CE
inputs will not result in a write cycle.
SOFTWARE DATA PROTECTION
The CAT28LV256 features a software controlled data
protection scheme which, once enabled, requires a data
algorithm to be issued to the device before a write can be
performed. The device is shipped from Catalyst with the
software protection NOT ENABLED (the CAT28LV256
is in the standard operating mode).
Figure 9. Write Sequence for Activating Software
Data Protection
WRITE DATA:
ADDRESS:
AA
5555
Figure 10. Write Sequence for Deactivating
Software Data Protection
WRITE DATA:
ADDRESS:
AA
5555
WRITE DATA:
ADDRESS:
55
2AAA
WRITE DATA:
ADDRESS:
55
2AAA
WRITE DATA:
ADDRESS:
A0
5555
WRITE DATA:
ADDRESS:
80
5555
SOFTWARE DATA
(1)
PROTECTION ACTIVATED
WRITE DATA:
ADDRESS:
AA
5555
WRITE DATA: XX
TO ANY ADDRESS
WRITE DATA:
ADDRESS:
55
2AAA
WRITE LAST BYTE
TO
LAST ADDRESS
28LV256 F12
WRITE DATA:
ADDRESS:
20
5555
28LV256 F13
Note:
(1) Write protection is activated at this point whether or not any more writes are completed. Writing to addresses must occur within t_BLC
Max., after SDP activation.
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Doc. No. 1071, Rev. B