CAT1026_07 Datasheet, PDF (9/20 Pages) Catalyst Semiconductor – Dual Voltage Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM

EMBEDDED EEPROM OPERATION
The CAT1026 and CAT1027 feature a 2-kbit embedded
serial EEPROM that supports the I²C Bus data
transmission protocol. This Inter-Integrated Circuit Bus
protocol defines any device that sends data to the bus to
be a transmitter and any device receiving data to be a
receiver. The transfer is controlled by the Master device
which generates the serial clock and all START and
STOP conditions for bus access. Both the Master device
and Slave device can operate as either transmitter
or receiver, but the Master device controls which mode
is activated.
I²C BUS PROTOCOL
The features of the I²C bus protocol are defined as
follows:
(1) Data transfer may be initiated only when the bus
is not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any
changes in the data line while the clock line is
high will be interpreted as a START or STOP
condition.
START CONDITION
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
CAT1026, CAT1027
SDA when SCL is HIGH. The CAT1026 and CAT1027
monitor the SDA and SCL lines and will not respond
until this condition is met.
STOP CONDITION
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must
end with a STOP condition.
DEVICE ADDRESSING
The Master begins a transmission by sending a
START condition. The Master sends the address of
the particular slave device it is requesting. The four
most significant bits of the 8-bit slave address are
programmable in metal and the default is 1010.
The last bit of the slave address specifies whether a
Read or Write operation is to be performed. When this
bit is set to 1, a Read operation is selected, and when
set to 0, a Write operation is selected.
After the Master sends a START condition and the
slave address byte, the CAT1026 and CAT1027
monitor the bus and responds with an acknowledge
(on the SDA line) when its address matches the
transmitted slave address. The CAT1026 and
CAT1027 then perform a Read or Write operation
depending on the R/¯W¯ bit.
Figure 3. Bus Timing
tF
tHIGH
tR
tLOW
tLOW
SCL
tSU:STA
tHD:DAT
tHD:STA
tSU:DAT
SDA IN
SDA OUT
tAA
tDH
tSU:STO
tBUF
Figure 4. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
tWR
STOP
CONDITION
9
START
CONDITION
ADDRESS
Doc. No. 3010 Rev. L