CAT1026_07 Datasheet, PDF(6/20 Page) Catalyst Semiconductor – Dual Voltage Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM

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CAT1026_07 Datasheet, PDF (6/20 Pages) Catalyst Semiconductor – Dual Voltage Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM

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CAT1026, CAT1027

VOLTAGE MONITOR AND RESET CIRCUIT AC CHARACTERISTICS

Symbol

tPURST

tRDP

tGLITCH

tWD

tRPD2

Parameter

Reset Timeout

VTH to RESET Output Delay

VCC Glitch Reject Pulse Width

Watchdod Timeout

VSENSE to VLOW Delay

Test Conditions Min Typ

Note 2

130 200

Note 3

Note 4, 5

Note 1

1.0

1.6

Note 5

POWER-UP TIMING (6), (7)

Symbol

tPUR

tPUW

Parameter

Power-Up to Read Operation

Power-Up to Write Operation

Test Conditions Min Typ

Max

270

2.1

Max

270

Units

Âµs

Units

AC TEST CONDITIONS

Parameter

Input Pulse Voltages

Input Rise and Fall Times

Input Reference Voltages

Output Reference Voltages

Output Load

Test Conditions

0.2VCC to 0.8VCC

10ns

0.3VCC, 0.7VCC

0.5VCC

Current Source: IOL = 3mA; CL = 100pF

RELIABILITY CHARACTERISTICS

Symbol

NEND(6)

TDR(6)

VZAP(6)

ILTH(6)(8)

Parameter

Endurance

Data Retention

ESD Susceptibility

Latch-Up

Reference Test Method

Min

Max

Units

MIL-STD-883, Test Method 1033 1,000,000

Cycles/Byte

MIL-STD-883, Test Method 1008

100

Years

MIL-STD-883, Test Method 3015

2000

Volts

JEDEC Standard 17

100

Notes:

(1) Test Conditions according to âAC Test Conditionsâ table.

(2) Power-up, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to âAC Test Conditionsâ Table

(3) Power-Down, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to âAC Test Conditionsâ Table

(4) VCC Glitch Reference Voltage = VTHmin; Based on characterization data

5) 0 < VSENSE - VCC, VLOW Output Reference Voltage and Load according to âAC Test Conditionsâ Table.

(6) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.

(7) tPUR and tPUW are the delays required from the time VCC is stable until the specified memory operation can be initiated.

(8) Latch-up protection is provided for stresses up to 100mA on input and output pins from -1 V to VCC + 1 V.

Doc. No. 3010 Rev. L

Characteristics subject to change without notice

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