CAT525_0711 Datasheet, PDF (8/16 Pages) Catalyst Semiconductor – Quad Digitally Programmable Potentiometer (DPP™) with 256 Taps and Microwire Interface

CAT525
following the D7 bit. Two clock cycles after the D7 bit
the DPP control register will be ready to receive the
next set of address and data bits. The clock must be
kept running throughout the programming cycle.
Internal control circuitry takes care of generating and
ramping up the programming voltage for data transfer
to the non-volatile memory cells. The CAT525’s non-
volatile memory cells will endure over 100,000 write
cycles and will retain data for a minimum of 20 years
without being refreshed.
READING DATA
Each time data is transferred into a DPP wiper control
register currently held data is shifted out via the D0
pin, thus in every data transaction a read cycle
occurs. Note, however, that the reading process is
destructive. Data must be removed from the register
in order to be read. Figure 2 depicts a Read Only
cycle in which no change occurs in the DPP’s output.
This feature allows µPs to poll DPPs for their current
setting without disturbing the output voltage but it
assumes that the setting being read is also stored in
non-volatile memory so that it can be restored at the
end of the read cycle. In Figure 2 CS returns low
before the 13^th clock cycle completes. In doing so the
non-volatile memory setting is reloaded into the DPP
wiper control register. Since this value is the same as
that which had been there previously no change in the
DPP’s output is noticed. Had the value held in the
control register been different from that stored in non-
volatile memory then a change would occur at the
read cycle’s conclusion.
TEMPORARILY CHANGE OUTPUT
The CAT525 allows temporary changes in DPP’s
output to be made without disturbing the settings
retained in non-volatile memory. This feature is
particularly useful when testing for a new output
setting and allows for user adjustment of preset or
default values without losing the original factory
settings.
Figure 3 shows the control and data signals needed to
effect a temporary output change. DPP settings may
be changed as many times as required and can be
made to any of the four DPPs in any order or
sequence. The temporary setting(s) remain in effect
long as CS remains high. When CS returns low all
four DPPs will return to the output values stored in
non-volatile memory.
When it is desired to save a new setting acquired
using this feature, the new value must be reloaded
into the DPP control register prior to programming.
This is because the CAT525’s internal control circuitry
discards from the programming register the new data
two clock cycles after receiving it if no PROG signal is
received.
Figure 2. Reading from Memory
t _o 1 2 3 4 5 6 7 8 9 10
11 12
CS
DI
1 A0 A1
CURRENT DPP DATA
DO
D0 D1 D2 D3 D4 D5 D6 D7
PROG
RDY/BSY
DPP
OUTPUT
CURRENT
DPP VALUE
NON-VOL ATILE
Figure 3. Temporary Change in Output
t o 1 2 3 4 5 6 7 8 9 10
11 12
N N+1 N+2
CS
DI
DO
PROG
RDY/BSY
DPP
OUTPUT
NEW DPP DATA
1 A0 A1 D0 D1 D2 D3 D4 D5 D6 D7
CURRENT DPP DATA
D0 D1 D2 D3 D4 D5 D6 D7
CURRENT
DPP VALUE
NON-VOL ATILE
NEW
DPP VALUE
VOLATILE
CURRENT
DPP VALUE
NON-VOL ATILE
Doc. No. MD-2001 Rev. H
8
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice