CAT525_0711 Datasheet, PDF (7/16 Pages) Catalyst Semiconductor – Quad Digitally Programmable Potentiometer (DPP™) with 256 Taps and Microwire Interface

CAT525
CLOCK
The CAT525’s clock controls both data flow in and out
of the IC and non-volatile memory cell programming.
Serial data is shifted into the DI pin and out of the DO
pin on the clock’s rising edge. While it is not
necessary for the clock to be running between data
transfers, the clock must be operating in order to write
to non-volatile memory, even though the data being
saved may already be resident in the DPP wiper
control register.
No clock is necessary upon system power-up. The
CAT525’s internal power-on reset circuitry loads data
from non-volatile memory to the DPPs without using
the external clock.
As data transfers are edge triggered clean clock
transitions are necessary to avoid falsely clocking
data into the control registers. Standard CMOS and
TTL logic families work well in this regard and it is
recommended that any mechanical switches used for
breadboarding or device evaluation purposes be
debounced by a flip-flop or other suitable debouncing
circuit.
V_REF
V_REF, the voltage applied between pins V_REFH & V_REFL,
sets the configured DPP’s Zero to Full Scale output
range where V_REFL = Zero and V_REFH = Full Scale.
V_REF can span the full power supply range or just a
fraction of it. In typical applications V_REFH & V_REFL are
connected across the power supply rails. When using
less than the full supply voltage be mindfull of the
limits placed on V_REFH and V_REFL as specified in the
References section of DC Electrical Characteristics.
READY/B¯¯U¯S¯Y¯
When saving data to non-volatile memory, the
Ready/Busy ouput (RDY/¯B¯S¯Y¯) signals the start and
duration of the erase/write cycle. Upon receiving a
command to store data (PROG goes high) RDY/¯B¯S¯Y¯
goes low and remains low until the programming cycle is
complete. During this time the CAT525 will ignore any
data appearing at DI and no data will be output on DO.
RDY/¯B¯S¯Y¯ is internally ANDed with a low voltage
detector circuit monitoring V_DD. If V_DD is below the
minimum value required for EEPROM programming,
RDY/¯B¯S¯Y¯ will remain high following the program
command indicating a failure to record the desired
data in non-volatile memory.
DATA OUTPUT
Data is output serially by the CAT525, LSB first, via
the Data Out (DO) pin following the reception of a
start bit and two address bits by the Data Input (DI).
DO becomes active whenever CS goes high and
resumes its high impedance Tri-State mode when CS
returns low. Tri-Stating the DO pin allows several
525s to share a single serial data line and simplifies
interfacing multiple 525s to a microprocessor.
WRITING TO MEMORY
Programming the CAT525’s non-volatile memory is
accomplished through the control signals: Chip Select
(CS) and Program (PROG). With CS high, a start bit
followed by a two bit DPP address and eight data bits
are clocked into the DPP wiper control register via the
DI pin. Data enters on the clock’s rising edge. The
DPP output changes to its new setting on the clock
cycle following D7, the last data bit.
Programming is accomplished by bringing PROG high
sometime after the start bit and at least 150 ns prior to
the falling edge of the clock cycle immediately
Figure 1. Writing to Memory
t _o 1 2 3 4 5 6 7 8 9 10
11 12
N N+1 N+2
CS
NEW DPP DATA
DI
1 A0 A1 D0 D1 D2 D3 D4 D5 D6 D7
CURRENT DPP DATA
DO
D0 D1 D2 D3 D4 D5 D6 D7
PROG
RDY/BSY
DPP
OUTPUT
CURRENT
DPP VALUE
NON-VOL ATILE
NEW
DPP VALUE
VOLATILE
NEW
DPP VALUE
NON-VOL ATILE
© Catalyst Semiconductor, Inc.
7
Characteristics subject to change without notice
Doc. No. MD-2001 Rev. H