CAT521_07 Datasheet, PDF (8/13 Pages) Catalyst Semiconductor – Configured Digitally Programmable Potentiometer (DPP™): Programmable Voltage Applications

CAT521
READING DATA
Each time data is transferred into the DPP wiper
control register currently held data is shifted out via
the D0 pin, thus in every data transaction a read cycle
occurs. Note, however, that the reading process is
destructive. Data must be removed from the register
in order to be read. Figure 2 depicts a Read Only
cycle in which no change occurs in the DPP’s output.
This feature allows µPs to poll DPPs for their current
setting without disturbing the output voltage but it
assumes that the setting being read is also stored in
non-volatile memory so that it can be restored at the
end of the read cycle. In Figure 2 CS returns low
before the 13^th clock cycle completes. In doing so the
non-volatile memory's setting is reloaded into the DPP
wiper control register. Since this value is the same as
that which had been there previously no change in the
DPP’s output is noticed. Had the value held in the
control register been different from that stored in non-
volatile memory then a change would occur at the
read cycle’s conclusion.
TEMPORARILY CHANGE OUTPUT
The CAT521 allows temporary changes in the DPP’s
output to be made without disturbing the settings
retained in non-volatile memory. This feature is
particularly useful when testing for a new output
setting and allows for user adjustment of preset or
default values without losing the original factory
settings.
Figure 3 shows the control and data signals needed to
effect a temporary output change. DPP settings may
be changed as many times as required. The
temporary setting remains in effect long as CS
remains high. When CS returns low the DPP will
return to the output value stored in non-volatile
memory.
When it is desired to save a new setting acquired
using this feature, the new value must be reloaded
into the DPP wiper control register prior to program-
ming. This is because the CAT521’s internal control
circuitry discards from the programming register the
new data two clock cycles after receiving it if no
PROG signal is received.
Figure 2. Reading from Memory
t _o 1 2 3 4 5 6 7 8 9 10
11 12
CS
DI
1 A0 A1
CURRENT DPP DATA
DO
D0 D1 D2 D3 D4 D5 D6 D7
PROG
RDY/BSY
DPP
OUTPUT
CURRENT
DPP VALUE
NON-VOL ATILE
Figure 3. Temporary Change in Output
t o 1 2 3 4 5 6 7 8 9 10
11 12
N N+1 N+2
CS
DI
DO
PROG
RDY/BSY
DPP
OUTPUT
NEW DPP DATA
1 A0 A1 D0 D1 D2 D3 D4 D5 D6 D7
CURRENT DPP DATA
D0 D1 D2 D3 D4 D5 D6 D7
CURRENT
DPP VALUE
NON-VOL ATILE
NEW
DPP VALUE
VOLATILE
CURRENT
DPP VALUE
NON-VOL ATILE
Doc. No. MD-2003 Rev. G
8
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice