CAT521_07 Datasheet, PDF (6/13 Pages) Catalyst Semiconductor – Configured Digitally Programmable Potentiometer (DPP™): Programmable Voltage Applications

CAT521
PIN DESCRIPTION
Pin Name Function
1
V_DD
Power supply positive
2
CLK Clock input pin
3 RDY/¯B¯S¯Y¯ Ready/Busy output
4
CS
Chip select
5
DI
Serial data input pin
6
DO
Serial data output pin
7
PROG
EEPROM Programming Enable
Input
8
GND Power supply ground
9
V_REFL Minimum DAC output voltage
10
NC
No Connect
11
NC
No Connect
12
V_OUT
DPP output
13
NC
No Connect
14 V_REFH Maximum DPP 1 output voltage
DPP addressing is as follows:
DPP OUTPUT
V_OUT
A0 A1
10
DEVICE OPERATION
The CAT521 is a single 8-bit configured digitally
programmable potentiometer (DPP™) whose output
can be programmed to any one of 256 individual
voltage steps. Once programmed, the output setting is
retained in non-volatile memory and will not be lost
when power is removed from the chip. Upon power up
the DPP returns to the setting stored in non-volatile
memory. The DPP can be written to and read from
without effecting the output voltage during the read or
write cycle. The output can also be adjusted without
altering the stored output setting, which is useful for
testing new output settings before storing them in
memory.
DIGITAL INTERFACE
The CAT521 employs a 3 wire, Microwire-like serial
control interface consisting of Clock (CLK), Chip
Select (CS) and Data In (DI) inputs. For all operations,
address and data are shifted in LSB first. In addition,
all digital data must be preceded by a logic “1” as a
start bit. The DPP address and data are clocked into
the DI pin on the clock’s rising edge. When sending
multiple blocks of information a minimum of two clock
cycles is required between the last block sent and the
next start bit.
Multiple devices may share a common input data line
by selectively activating the CS control of the desired
IC. Data Outputs (DO) can also share a common line
because the DO pin is Tri-Stated and returns to a high
impedance when not in use.
CHIP SELECT
Chip Select (CS) enables and disables the CAT521’s
read and write operations. When CS is high data may
be read to or from the chip, and the Data Output (DO)
pin is active. Data loaded into the DPP control register
will remain in effect until CS goes low. Bringing CS to
a logic low returns all DPP outputs to the settings
stored in nonvolatile memory and switches DO to its
high impedance Tri-State mode.
Because CS functions like a reset the CS pin has
been desensitized with a 30ns to 90ns filter circuit to
prevent noise spikes from causing unwanted resets
and the loss of volatile data.
CLOCK
The CAT521 clock controls both data flow in and out
of the device and non-volatile memory cell program-
ming. Serial data is shifted into the DI pin and out of
the DO pin on the clock’s rising edge. While it is not
necessary for the clock to be running between data
transfers, the clock must be operating in order to write
to non-volatile memory, even though the data being
saved may already be resident in the DPP wiper
control register.
No clock is necessary upon system power-up. The
CAT521 internal power-on reset circuitry loads data
Doc. No. MD-2003 Rev. G
6
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice