CAT34AC02 Datasheet, PDF (8/10 Pages) Catalyst Semiconductor – 2K-Bit SMBus EEPROM for ACR Card Configuration

CAT34AC02
Figure 9. Memory Array
FFH
Hardware Write Protectable
(by connecting WP pin to Vcc)
00H
Figure 10. Selective Read Timing
S
S
T
T
S
BUS ACTIVITY: ^A
SLAVE
BYTE
A
SLAVE
T
MASTER ^R ADDRESS
ADDRESS (n) ^R ADDRESS
O
T
T
P
SDA LINE S
S
*
A
A
C
C
K
K
P
A
N
C ^{DATA n}
O
K
A
C
K
5020 FHD F11
Figure 11. Sequential Read Timing
BUS ACTIVITY: SLAVE
MASTER ADDRESS
DATA n
SDA LINE
A
C
K
DATA n+1
DATA n+2
A
A
A
C
C
C
K
K
K
DATA n+x
S
T
O
P
P
N
O
A
C
K
5020 FHD F12
Doc. No. 1025, Rev. E
8