CAT34AC02 Datasheet, PDF (3/10 Pages) Catalyst Semiconductor – 2K-Bit SMBus EEPROM for ACR Card Configuration

CAT34AC02
A.C. CHARACTERISTICS
V_CC = +1.8V to +6.0V, unless otherwise specified.
Read & Write Cycle Limits
Symbol Parameter
1.8V-6.0V, 2.5V - 6.0V
Min
Max
F_SCL
Clock Frequency
100
T (1)
I
Noise Suppression Time Constant at
SCL, SDA Inputs
100
t_AA
SCL Low to SDA Data Out
and ACK Out
3.5
t ⁽¹⁾
BUF
Time the Bus Must be Free Before a
New Transmission Can Start
4.7
t
Start Condition Hold Time
4
HD:STA
t_LOW
Clock Low Period
4.7
t_HIGH
Clock High Period
4
t_SU:STA
Start Condition Setup Time (for a
Repeated Start Condition)
4.7
t_HD:DAT
t_SU:DAT
t ⁽¹⁾
R
t ⁽¹⁾
F
t_SU:STO
t_DH
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
0
50
1
300
4
100
Power-Up Timing⁽¹⁾⁽²⁾
Symbol Parameter
Min
t_PUR
tPUW
Power-up to Read Operation
Power-up to Write Operation
Write Cycle Limits
Symbol Parameter
Min
tWR
Write Cycle Time
4.5V - 5.5V
Min
Max
400
100
1
1.2
0.6
1.2
0.6
0.6
0
50
0.3
300
0.6
100
Typ
Max
1
1
Typ
Max
4
5
Units
kHz
ns
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
µs
ns
Units
ms
ms
Units
ms
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t_PUR and t_PUW are the delays required from the time V_CC is stable until the specified operation can be initiated.
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Doc No. 1025, Rev. E