CAT25C08_06 Datasheet, PDF (8/16 Pages) Catalyst Semiconductor – 8K/16K SPI Serial CMOS EEPROM

CAT25C08/16
Byte Write
Once the device is in a Write Enable state, the user may
proceed with a write sequence by setting the CS low,
issuing a write instruction via the SI line, followed by the
16-bit address for 25C08/16. (only 10-bit addresses are
used for 25C08, 11-bit addresses are used for 25C16.
The rest of the bits are don't care bits). Programming will
start after the CS is brought high. Figure 6 illustrates
byte write sequence. During an internal write cycle, all
commands will be ignored except the RDSR (Read
Status Register) instruction.
The Status Register can be read to determine if the write
cycle is still in progress. If Bit 0 of the Status Register is
set at 1, write cycle is in progress. If Bit 0 is set at 0, the
device is ready for the next instruction
Page Write
The CAT25C08/16 features page write capability. After
the initial byte, the host may continue to write up to 32
bytes. After each byte of data received, lower order
address bits are internally incremented by one; the high
order bits of address will remain constant.The only
restriction is that the 32 bytes must reside on the same
page. If the address counter reaches the end of the
page and clock continues, the counter will “roll over” to
the first address of the page and overwrite any data that
may have been written. The CAT25C08/16 is automati-
cally returned to the write disable state at the completion
of the write cycle. Figure 8 illustrates the page write
sequence.
To write to the status register, the WRSR instruction
should be sent. Only Bit 2, Bit 3 and Bit 7 of the status
register can be written using the WRSR instruction.
Figure 7 illustrates the sequence of writing to status
register.
Figure 5. RDSR Instruction Timing
CS
SCK
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14
OPCODE
SI
0
0
0
0
0
SO
HIGH IMPEDANCE
Note: Dashed Line= mode (1, 1) – – – – –
1
0
1
DATA OUT
7
6
5
4
32
10
MSB
Figure 6. Write Instruction Timing
CS
SCK
012345678
*
21 22 23 24 25 26 27 28 29 30 31
OPCODE
BYTE ADDRESS*
DATA IN
SI
0 0 0 0 0 0 1 0 ^AN
A0 _{D7 D6 D5 D4 D3 D2 D1 D0}
SO
HIGH IMPEDANCE
*Please check the Byte Address Table
Note: Dashed Line= mode (1, 1) – – – – –
Doc. No. 1016, Rev. C
8
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice