CAT34WC02 Datasheet, PDF (7/10 Pages) Catalyst Semiconductor – 2K-Bit I2C Serial EEPROM, Serial Presence Detect

CAT34WC02
memory array is protected and becomes read only. The
entire memory becomes write protected regardless of
whether the write protect register has been written or
not. When WP pin is tied to Vcc, the user cannot program
the write protect register. If the WP pin is left floating or
tied to Vss, the device can be written into (except the first
128 bytes if the write protect register is programmed).
Software
The software protection on the CAT34WC02 protects
the first 128 bytes of the memory array permanently.
Software write protect is implemented by programming
the write protect register. A user can write only once to
the write protect register and once written it is irrevers-
ible (even if you reset the CAT34WC02).
The write protection register is written by sending a
regular byte write command with the slave address set
to 0110 instead of 1010. After the initial acess to the
register, the device will not acknowledge any further
access to this register.
READ OPERATIONS
The READ operation for the CAT34WC02 is initiated in
the same manner as the write operation with the one
exception that the R/W bit is set to a one. Three different
READ operations are possible: Immediate Address
READ, Selective READ and Sequential READ.
Immediate Address Read
The CAT34WC02’s address counter contains the ad-
dress of the last byte accessed, incremented by one. In
other words, if the last READ or WRITE access was to
address N, the READ immediately following would ac-
cess data from address N+1. If N = 255 for 34WC02,
then the counter will ‘wrap around’ to address 0 and
continue to clock out data. After the CAT34WC02 re-
ceives its slave address information (with the R/W bit set
to one), it issues an acknowledge, then transmits the 8-
bit byte requested. The master device does not send an
acknowledge but will generate a STOP condition.
Selective Read
Selective READ operations allow the Master device to
select at random any memory location for a READ
operation. The Master device first performs a ‘dummy’
write operation by sending the START condition, slave
address and byte address of the location it wishes to
read. After the CAT34WC02 acknowledge the word
address, the Master device resends the START condi-
tion and the slave address, this time with the R/W bit set
to one. The CAT34WC02 then responds with its ac-
knowledge and sends the 8-bit byte requested. The
master device does not send an acknowledge but will
generate a STOP condition.
Sequential Read
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT34WC02 sends the initial 8-bit
data requested, the Master will respond with an ac-
knowledge which tells the device it requires more data.
The CAT34WC02 will continue to output a byte for each
acknowledge sent by the Master. The operation will
terminate operation when the Master fails to respond
with an acknowledge, thus sending the STOP condition.
The data being transmitted from the CAT34WC02 is
outputted sequentially with data from address N fol-
lowed by data from address N+1. The READ operation
address counter increments all of the CAT34WC02
address bits so that the entire memory array can be read
during one operation. If more than the 256 bytes are read
out, the counter will “wrap around” and continue to clock
out data bytes.
Figure 8. Immediate Address Read Timing
S
T
S
BUS ACTIVITY: ^A
SLAVE
T
MASTER ^R ADDRESS
O
T
P
SDA LINE S
P
A
N
C
DATA
O
K
K
A
C
K
SCL
8
9
SDA
8TH BIT
DATA OUT
NO ACK
7
STOP
5020 FHD F10
Doc No. 1003, Rev. A