CAT28C64BJ-12 Datasheet, PDF (7/12 Pages) Catalyst Semiconductor – 64K-Bit CMOS PARALLEL E2PROM

CAT28C64B
DEVICE OPERATION
Read
Data stored in the CAT28C64B is transferred to the data
bus when WE is held high, and both OE and CE are held
low. The data bus is set to a high impedance state when
either CE or OE goes high. This 2-line control architec-
ture can be used to eliminate bus contention in a system
environment.
Byte Write
A write cycle is executed when both CE and WE are low,
and OE is high. Write cycles can be initiated using either
WE or CE, with the address input being latched on the
falling edge of WE or CE, whichever occurs last. Data,
conversely, is latched on the rising edge of WE or CE,
whichever occurs first. Once initiated, a byte write cycle
automatically erases the addressed byte and the new
data is written within 5 ms.
Figure 3. Read Cycle
ADDRESS
CE
OE
WE
DATA OUT
tRC
tCE
tOE
VIH
tLZ
HIGH-Z
tOLZ
tOH
DATA VALID
tAA
Figure 4. Byte Write Cycle [WE Controlled]
ADDRESS
tAS
tAH
tCS
tCH
CE
tOHZ
tHZ
DATA VALID
tWC
28C64B F06
OE
WE
DATA OUT
DATA IN
tOES
tWP
HIGH-Z
tOEH
tBLC
DATA VALID
tDS
tDH
7
5096 FHD F06
Doc. No. 25006-0A 2/98 P-1