CAT28C64BJ-12 Datasheet, PDF (10/12 Pages) Catalyst Semiconductor – 64K-Bit CMOS PARALLEL E2PROM

CAT28C64B
HARDWARE DATA PROTECTION
The following is a list of hardware data protection fea-
tures that are incorporated into the CAT28C64B.
(1) VCC sense provides for write protection when VCC
falls below 3.5V min.
(2) A power on delay mechanism, t_INIT (see AC charac-
teristics), provides a 5 to 10 ms delay before a write
sequence, after V_CC has reached 3.5V min.
(3) Write inhibit is activated by holding any one of OE
low, CE high or WE high.
(4) Noise pulses of less than 20 ns on the WE or CE
inputs will not result in a write cycle.
SOFTWARE DATA PROTECTION
The CAT28C64B features a software controlled data
protection scheme which, once enabled, requires a data
algorithm to be issued to the device before a write can be
performed. The device is shipped from Catalyst with the
software protection NOT ENABLED (the CAT28C64B is
in the standard operating mode).
Figure 9. Write Sequence for Activating Software
Data Protection
WRITE DATA:
ADDRESS:
AA
1555
Figure 10. Write Sequence for Deactivating
Software Data Protection
WRITE DATA:
ADDRESS:
AA
1555
WRITE DATA:
ADDRESS:
55
0AAA
WRITE DATA:
ADDRESS:
55
0AAA
WRITE DATA:
ADDRESS:
A0
1555
WRITE DATA:
ADDRESS:
80
1555
SOFTWARE DATA ₍₁₎
PROTECTION ACTIVATED
WRITE DATA:
ADDRESS:
AA
1555
WRITE DATA: XX
TO ANY ADDRESS
WRITE LAST BYTE
TO
LAST ADDRESS
28C64B F12
WRITE DATA:
ADDRESS:
55
0AAA
WRITE DATA:
ADDRESS:
20
1555
5094 FHD F09
Note:
(1) Write protection is activated at this point whether or not any more writes are completed. Writing to addresses must occur within t_BLC
Max., after SDP activation.
Doc. No. 25006-0A 2/98 P-1
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