CAT25020 Datasheet, PDF (7/18 Pages) Catalyst Semiconductor – 1K/2K/4K SPI Serial CMOS EEPROM

CAT25010, CAT25020, CAT25040
to provide clock pulses. The internal address pointer is
automatically incremented to the next higher address
after each byte of data is shifted out. When the highest
address is reached, the address counter rolls over to
0000h allowing the read cycle to be continued indefinitely.
The read operation is terminated by pulling the CS high.
Read sequece is illustrated in Figure 4.
To read the status register, RDSR instruction should be
sent. The contents of the status register are shifted out
on the SO line. The status register may be read at any
time even during a write cycle. Reading status register
is illustrated in Figure 5.
WRITE Sequence
The CAT25010/20/40 powers up in a Write Disable
state. Prior to any write instructions, the WREN instruction
must be sent to CAT25010/20/40. The device goes into
Write enable state by pulling the CS low and then
clocking the WREN instruction into CAT25010/20/40.
The CS must be brought high after the WREN instruction
to enable writes to the device. If the write operation is
initiated immediately after the WREN instruction without
CS being brought high, the data will not be written to the
array because the write enable latch will not have been
properly set. Also, for a successful write operation the
Figure 4. Read Instruction Timing
CS
SCK
SI
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
OPCODE
BYTE ADDRESS
0 0 0 0 X0* 0 1 1 A7 A6 A5 A4 A3 A2 A1 A0
SO
HIGH IMPEDANCE
*Please check the instruction set table for address
X=0 for 25010, 25020 ; X=A8 for 25040
Note: Dashed line = mode (1,1)----
DATA OUT
D7 D6 D5 D4 D3 D2 D1 D0
MSB
Figure 5. RDSR Instruction Timing
CS
SCK
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14
OPCODE
SI
0
0
0
0
0
SO
HIGH IMPEDANCE
Note: Dashed Line= mode (1, 1) – – – – –
1
0
1
DATA OUT
7
6
5
4
3
2
10
MSB
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
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Doc. No. 1006, Rev. S