CAT24WC128 Datasheet, PDF (7/8 Pages) Catalyst Semiconductor – 128K-Bit I2C Serial CMOS E2PROM

Preliminary
CAT24WC128
READ operation. The Master device first performs a
‘dummy’ write operation by sending the START condi-
tion, slave address and byte addresses of the location it
wishes to read. After CAT24WC128 acknowledges, the
Master device sends the START condition and the slave
address again, this time with the R/W bit set to one. The
CAT24WC128 then responds with its acknowledge and
sends the 8-bit byte requested. The master device does
not send an acknowledge but will generate a STOP
condition.
Sequential Read
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT24WC128 sends the initial 8-
bit byte requested, the Master will respond with an
acknowledge which tells the device it requires more
Figure 8. Immediate Address Read Timing
data. The CAT24WC128 will continue to output an 8-bit
byte for each acknowledge sent by the Master. The
operation will terminate when the Master fails to re-
spond with an acknowledge, thus sending the STOP
condition.
The data being transmitted from CAT24WC128 is out-
putted sequentially with data from address N followed
by data from address N+1. The READ operation ad-
dress counter increments all of the CAT24WC128 ad-
dress bits so that the entire memory array can be read
during one operation. If more than E (where E=16383)
bytes are read out, the counter will ‘wrap around’ and
continue to clock out data bytes.
S
T
BUS ACTIVITY: ^A SLAVE
MASTER ^R ADDRESS
T
S
T
DATA
O
P
SDA LINE S
P
A
N
C
O
K
A
C
K
SCL
8
9
SDA
8TH BIT
DATA OUT
NO ACK
STOP
24WC128 F10
Figure 9. Selective Read Timing
S
T
BUS ACTIVITY: ^A
MASTER ^R
T
SDA LINE S
SLAVE
ADDRESS
BYTE ADDRESS
A15–A8
A7–A0
**
A
A
C
C
K
K
*=Don't Care Bit
7
S
T
A _SLAVE
R _ADDRESS
T
S
A
A
C
C
K
K
DATA
S
T
O
P
P
N
O
A
C
K
24WC128 F11
Doc. No. 25060-00 6/99 S-1