CAT24WC128 Datasheet, PDF (3/8 Pages) Catalyst Semiconductor – 128K-Bit I2C Serial CMOS E2PROM

Preliminary
CAT24WC128
A.C. CHARACTERISTICS
V_CC = +1.8V to +6V, unless otherwise specified
Output Load is 1 TTL Gate and 100pF
Read & Write Cycle Limits
Symbol Parameter
V_CC=1.8V - 6.0V V_CC=2.5V - 6.0V V_CC=3.0V - 5.5V
Min. Max. Min. Max. Min. Max. Units
F_SCL
Clock Frequency
100
400
1000 kHz
t_AA
SCL Low to SDA Data Out
and ACK Out
0.1 3.5
0.05 0.9
0.05 0.55 µs
t_BUF(1) Time the Bus Must be Free Before 4.7
1.2
a New Transmission Can Start
0.5
µs
t_HD:STA Start Condition Hold Time
4.0
0.6
0.25
µs
t_LOW
Clock Low Period
4.7
1.2
0.6
µs
t_HIGH
Clock High Period
4.0
0.6
0.4
µs
t_SU:STA Start Condition Setup Time
4.0
0.6
(for a Repeated Start Condition)
0.25
µs
t_HD:DAT Data In Hold Time
0
0
0
ns
t_SU:DAT
t_R(1)
t_F(1)
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
100
1.0
300
100
0.3
300
100
ns
0.3
µs
100
ns
t_SU:STO Stop Condition Setup Time
4.7
0.6
0.25
µs
t_DH
Data Out Hold Time
100
50
50
ns
t_WR
Write Cycle Time
10
10
10
ms
Power-Up Timing ⁽¹⁾⁽²⁾
Symbol
Parameter
Max.
Units
tPUR
tPUW
Power-Up to Read Operation
Power-Up to Write Operation
1
ms
1
ms
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t_PUR and t_PUW are the delays required from the time V_CC is stable until the specified operation can be initiated.
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During
the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave
address.
FUNCTIONAL DESCRIPTION
The CAT24WC128 supports the I²C Bus data transmis-
sion protocol. This Inter-Integrated Circuit Bus protocol
defines any device that sends data to the bus to be a
transmitter and any device receiving data to be a re-
ceiver. The transfer is controlled by the Master device
which generates the serial clock and all START and
STOP conditions for bus access. The CAT24WC128
operates as a Slave device. Both the Master device and
Slave device can operate as either transmitter or re-
ceiver, but the Master device controls which mode is
activated.
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Doc. No. 25060-00 6/99 S-1