CAT93HC46_05 Datasheet, PDF (6/9 Pages) Catalyst Semiconductor – 1-kb High Speed Microwire Serial EEPROM

CAT93HC46
Erase/Write Enable and Disable
Write All
The CAT93HC46 powers up in the write disable state. Upon receiving a WRAL command and data, the CS
Any writing after power-up or after an EWDS (write (Chip Select) pin must be deselected for a minimum of
disable) instruction must first be preceded by the EWEN tCSMIN. The falling edge of CS will start the self-timed
(write enable) instruction. Once write is enabled, it will data write to all memory locations in the device. The
remain enabled until power to the device is removed, or clocking of the SK pin is not necessary after the device
the EWDS instruction is sent. The EWDS instruction can has entered the self-timed mode. The ready/busy status
be used to disable all CAT93HC46 write and clear of the CAT93HC46 can be determined by selecting the
instructions, and will prevent any accidental writing or device and polling the DO pin. It is not necessary for all
clearing of the device. Data can be read normally from
the device regardless of the write enable/disable status.
Erase All
t _{Upon receiving an ERAL command, the CS (Chip Select)}
r pin must be deselected for a minimum of tCSMIN. The
falling edge of CS will start the self-timed clear cycle of
a ^{all memory locations in the device. The clocking of the}
SK pin is not necessary after the device has entered the
self-timed mode. (Note 1.) The ready/busy status of the
P _{CAT93HC46 can be determined by selecting the device}
and polling the DO pin. Once cleared, the contents of all
memory locations will return to a logical “1” state.
memory locations to be cleared before the WRAL
command is executed. Once written, the contents of all
memory locations will return to a logical “0” state.
Note 1: After the last data bit has been sampled, Chip
Select (CS) must be brought Low before the next rising
edge of the clock (SK) in order to start the self-timed high
voltage cycle. This is important because if the CS is
brought low before or after this specific frame window,
the addressed location will not be programmed or erased.
d _{Figure 3. Write Instruction Timing}
e _SK
u _CS
tin ^{AN AN-1}
DI
101
A0 DN
nHIGH-Z
DO
tCS _MIN
STATUS
VERIFY
D0
STANDBY
tSV
BUSY
READY
tEW
tHZ
HIGH-Z
co _{Figure 4. Erase Instruction Timing}
Dis ^SK
CS
STATUS VERIFY
STANDBY
AN AN-1
DI
111
A0
tCS _MIN
tSV
tHZ
HIGH-Z
DO
BUSY READY
HIGH-Z
tEW
Doc. No. 1008, Rev. H
6