CAT93HC46_05 Datasheet, PDF (4/9 Pages) Catalyst Semiconductor – 1-kb High Speed Microwire Serial EEPROM

CAT93HC46
DEVICE OPERATION
The CAT93HC46 is a 1024-bit nonvolatile memory The ready/busy status can be determined after the start
intended for use with industry standard microprocessors. of a write operation by selecting the device (CS high) and
The CAT93HC46 can be organized as registers of either polling the DO pin; DO low indicates that the write
16 bits or 8 bits. When organized as X16, seven 9-bit operation is not completed, while DO high indicates that
instructions control the reading, writing and erase the device is ready for the next instruction. If necessary,
operations of the device. When organized as X8, seven the DO pin may be placed back into a high impedance
10-bit instructions control the operation of the device. state by shifting a dummy “1” into the DI pin. The DO pin
The CAT93HC46 operates on a single power supply and will enter the high impedance state on the falling edge of
will generate on chip the high voltage required during
write operation.
Instructions, addresses, and data are clocked into the DI
t pin on the rising edge of the clock (SK). The DO pin is
normally in a high impedance state, except when reading
r _{data from the device, or when checking the ready/busy}
status after a write operation.
Pa _{INSTRUCTION SET}
the clock (SK). Placing the DO pin into the high impedance
state is recommended in applications where the DI pin
and the DO pin are to be tied together to form a common
DI/O pin.
The format for all instructions sent to the device is a
logical "1" start bit, a 2-bit (or 4-bit) opcode, 6-bit byte/
word address (an additional bit when organized X8) and
for write operations a 16-bit data field (8-bit for X8
organization).
d _Instruction
e _READ
u ERASE
WRITE
tin ^EWEN
EWDS
ERAL
n _WRAL
Start
Address
Bit Opcode x8
x16
1
10 A6-A0 A5-A0
1
11 A6-A0 A5-A0
1
01 A6-A0 A5-A0
1
00 11XXXXX 11XXXX
1
00 00XXXXX 00XXXX
1
00 10XXXXX 10XXXX
1
00 01XXXXX 01XXXX
Data
x8
x16 Comments
Read Address AN–A0
Clear Address AN–A0
D7-D0 D15-D0 Write Address AN–A0
Write Enable
Write Disable
Clear All Addresses
D7-D0 D15-D0 Write All Addresses
co _{Figure 1. Sychronous Data Timing}
is _tSKHI
D^SK
tSKLOW
tCSH
tDIS
DI
VALID
VALID
tDIH
tCSS
CS
tDIS
tPD0,tPD1
tCSMIN
DO
DATA VALID
Doc. No. 1008, Rev. H
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