CAT93C66_07 Datasheet, PDF (6/17 Pages) Catalyst Semiconductor – 4-Kb Microwire Serial CMOS EEPROM

CAT93C66
Read
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAT93C66
will come out of the high impedance state and, after
sending an initial dummy zero bit, will begin shifting
out the data addressed (MSB first). The output data
bits will toggle on the rising edge of the SK clock and
are stable after the specified time delay (t_PD0 or t_PD1).
For the CAT93C66, after the initial data word has
been shifted out and CS remains asserted with the SK
clock continuing to toggle, the device will auto-
matically increment to the next address and shift out
the next data word in a sequential READ mode. As
long as CS is continuously asserted and SK continues
to toggle, the device will keep incrementing to the next
address automatically until it reaches to the end of the
address space, then loops back to address 0. In the
sequential READ mode, only the initial data word is
preceeded by a dummy zero bit. All subsequent data
words will follow without a dummy zero bit. The READ
instruction timing is illustrated in Figure 2.
Erase/Write Enable and Disable
The CAT93C66 powers up in the write disable state. Any
writing after power-up or after an EWDS (erase/write
disable) instruction must first be preceded by the EWEN
(erase/write enable) instruction. Once the write
instruction is enabled, it will remain enabled until power
to the device is removed, or the EWDS instruction is
sent. The EWDS instruction can be used to disable all
CAT93C66 write and erase instructions, and will prevent
any accidental writing or clearing of the device. Data can
be read normally from the device regardless of the write
enable/disable status. The EWEN and EWDS
instructions timing is shown in Figure 3.
Figure 1. Sychronous Data Timing
tSKHI
SK
tDIS
DI
VALID
tCSS
CS
DO
tSKLOW
VALID
tDIH
tCSH
tDIS
tPD0,tPD1
tCSMIN
DATA VALID
Figure 2. READ Instruction Timing
SK
CS
AN AN–1
A0
DI
11
0
t_PD0
HIGH-Z
DO
Don't Care
Dummy 0
D15 _{. . .} D0
or
D7 _{. . .} D0
Address + 1
D15 _{. . .} D0
or
D7 _{. . .} D0
Address + 2
D15 _{. . .} D0
or
D7 _{. . .} D0
Address + n
D15 _{. . .}
or
D7 _{. . .}
Doc. No. 1089 Rev. P
6
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice