CAT35C704 Datasheet, PDF (6/14 Pages) Catalyst Semiconductor – 4K-Bit Secure Access Serial E2PROM

CAT35C704
Preliminary
CLK
The System Clock is a TTL compatible input pin that
allows operation of the device over a frequency range of
DC to 3 MHz.
DI
The Data Input pin is TTL compatible and accepts data
and instructions in a serial format. Each instruction must
begin with “1” as a start bit. The device will accept as
many bytes as an instruction requires, including both
data and address bytes. With the SECS protocol, extra
bits will be disregarded if they are “0”s and misinter-
preted as the next instruction if they are “1”s. An instruc-
tion error will cause the device to abort operation and all
I/O communication will be terminated until a reset is
received.
Figure 5. Program/Erase Timing
CS
tCKH
CLK
DI
LAST ADDRESS BIT FOR ERASE
LAST OPCODE BIT FOR ERAL
LAST DATA BIT FOR WRITE/WRAL
DO
HIGH-Z
tEW
tPD
DO
The Data Output pin is a tri-state TTL compatible output.
It is normally in a high impedance state unless a READ
or an ENABLE BUSY instruction is executed. Following
the completion of a 16-bit or 8-bit data stream, the output
will return to the high impedance state. During a pro-
gram/erase cycle, if the ENABLE BUSY instruction has
been previously executed, the output will stay LOW
while the device is BUSY, and it will be set HIGH when
the program/erase cycle is completed. DO will stay
HIGH until the completion of the next instruction’s op-
code and, if the next instruction is a READ, DO will output
the appropriate data at the end of the instruction. If the
ENABLE BUSY instruction has not been previously
executed, DO will stay in a high impedance state. DO will
NEXT INSTRUCTION
5074 FHD F07
Figure 6. CS to DO Status Timing
CS
CLK
DI
LAST ADDRESS BIT FOR ERASE
LAST OPCODE BIT FOR ERAL
LAST DATA BIT FOR WRITE/WRAL
DO
HIGH-Z
NEXT INSTRUCTION
tCSZ
tCSD
READY
BUSY HIGH-Z BUSY
5074 FHD F08
Doc. No. 25045-00 2/98
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