CAT24WC129_04 Datasheet, PDF (6/9 Pages) Catalyst Semiconductor – 128K-Bit I2C Serial CMOS EEPROM

CAT24WC129
acknowledge, and internally increment the six low order read only. The CAT24WC129 will accept both slave and
address bits by one. The high order bits remain un- byte addresses, but the memory location accessed is
changed.
protected from programming by the device’s failure to
If the Master transmits more than 64 bytes before sending
the STOP condition, the address counter ‘wraps around’,
send an acknowledge after the first byte of data is
received.
and previously transmitted data will be overwritten.
READ OPERATIONS
When all 64 bytes are received, and the STOP condition
has been sent by the Master, the internal programming
The READ operation for the CAT24WC129 is initiated in
cycle begins. At this point, all received data is written to
the CAT24WC129 in a single write cycle.
Acknowledge Polling
t ^{Disabling of the inputs can be used to take advantage of}
the typical write cycle time. Once the stop condition is
r _{issued to indicate the end of the host's write operation,}
CAT24WC129 initiates the internal write cycle. ACK
a _{polling can be initiated immediately. This involves issu-}
ing the start condition followed by the slave address for
a write operation. If CAT24WC129 is still busy with the
P _{write operation, no ACK will be returned. If}
CAT24WC129 has completed the write operation, an
ACK will be returned and the host can then proceed with
d _{the next read or write operation.}
e _{WRITE PROTECTION}
u ^{The Write Protection feature allows the user to protect}
against inadvertent programming of the memory array.
If the WP pin is tied to V_CC, the top 1/4 array of memory
tin ^{(locations 3000H to 3FFFH) is protected and becomes}
Figure 6. Byte Write Timing
the same manner as the write operation with one excep-
tion, that R/W bit is set to one. Three different READ
operations are possible: Immediate/Current Address
READ, Selective/Random READ and Sequential READ.
Immediate/Current Address Read
The CAT24WC129’s address counter contains the ad-
dress of the last byte accessed, incremented by one. In
other words, if the last READ or WRITE access was to
address N, the READ immediately following would ac-
cess data from address N+1. If N=E (where E=16383),
then the counter will ‘wrap around’ to address 0 and
continue to clock out data. After the CAT24WC129
receives its slave address information (with the R/W bit
set to one), it issues an acknowledge, then transmits the
8 bit byte requested. The master device does not send
an acknowledge, but will generate a STOP condition.
Selective/Random Read
Selective/Random READ operations allow the Master
device to select at random any memory location for a
READ operation. The Master device first performs a
n _S
T
o BUS ACTIVITY: A SLAVE
MASTER ^R ADDRESS
T
BYTE ADDRESS
A15–A8
A7–A0
S
T
DATA
O
P
c SDA LINE _S
Dis ^{*=Don't Care Bit}
**
A
A
C
C
K
K
P
A
A
C
C
K
K
Figure 7. Page Write Timing
S
T
BUS ACTIVITY: ^A SLAVE
MASTER ^R ADDRESS
T
BYTE ADDRESS
A15–A8
A7–A0
DATA
DATA n
S
T
DATA n+63
O
P
SDA LINE S
**
P
A
A
A
A
AA
A
C
C
C
C
CC
C
K
K
K
K
KK
K
*=Don't Care Bit
Doc. No. 1079, Rev. V
6