CAT24FC17 Datasheet, PDF (6/10 Pages) Catalyst Semiconductor – 16-kb I2C Serial EEPROM

CAT24FC17
WRITE OPERATIONS
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/W bit set to zero) to the Slave device. After
the Slave generates an acknowledge, the Master sends
the byte address that is to be written into the address
pointer of the CAT24FC17. After receiving another
acknowledge from the Slave, the Master device transmits
the data byte to be written into the addressed memory
location. The CAT24FC17 acknowledges once more
and the Master generates the STOP condition, at which
time the device begins its internal programming to
nonvolatile memory. While this internal cycle is in
progress, the device will not respond to any request from
the Master device.
Page Write
The CAT24FC17 writes up to 16 bytes of data in a single
write cycle, using the Page Write operation. The Page
Write operation is initiated in the same manner as the
Byte Write operation, however instead of terminating
after the initial word is transmitted, the Master is allowed
to send up to 15 additional bytes. After each byte has
been transmitted the CAT24FC17 will respond with an
acknowledge, and internally increment the low order
address bits by one. The high order bits remain
unchanged.
If the Master transmits more than 16 bytes prior to
sending the STOP condition, the address counter ‘wraps
around’, and previously transmitted data will be
overwritten.
Once all 16 bytes are received and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point all received data is written to
the CAT24FC17 in a single write cycle.
Acknowledge Polling
The disabling of the inputs can be used to take advantage
of the typical write cycle time. Once the stop condition
is issued to indicate the end of the host’s write operation,
the CAT24FC17 initiates the internal write cycle. ACK
polling can be initiated immediately. This involves
issuing the start condition followed by the slave address
for a write operation. If the CAT24FC17 is still busy with
the write operation, no ACK will be returned. If the
CAT24FC17 has completed the write operation, an ACK
will be returned and the host can then proceed with the
next read or write operation.
WRITE PROTECTION
The CAT24FC17 is designed with a hardware protect
pin that enables the user to protect the upper half of the
memory. The hardware protection feature of the
CAT24FC17 is designed into the part to provide added
flexibility to the design engineers. The write protection
feature of CAT24FC17 allows the user to protect against
inadvertent programming of memory locations 400 H to
7 FFH. If the WP pin is tied to Vcc, the upper half of the
memory array is protected and becomes read only. If the
WP pin is left floating or tied to Vss, the device can be
written into.
Figure 6. Byte Write Timing
S
T
BUS ACTIVITY: ^A
MASTER ^R
T
SLAVE
ADDRESS
BYTE
ADDRESS
S
T
DATA
O
P
SDA LINE S
P
A
A
A
C
C
C
K
K
K
Figure 7. Page Write Timing
S
T
BUS ACTIVITY: ^A
SLAVE
MASTER ^R ADDRESS
T
BYTE
ADDRESS (n)
DATA n
DATA n+1
S
T
DATA n+P ^O
P
SDA LINE S
*
P
A
A
A
A
A
C
C
C
C
C
K
K
K
K
K
NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0
Doc. No. 1077, Rev. F
6
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice