CAT24FC17 Datasheet, PDF (4/10 Pages) Catalyst Semiconductor – 16-kb I2C Serial EEPROM

CAT24FC17
FUNCTIONAL DESCRIPTION
The CAT24FC17 supports the I²C Bus data transmission
protocol. This Inter-Integrated Circuit Bus protocol defines
any device that sends data to the bus to be a transmitter
and any device receiving data to be a receiver. Data
transfer is controlled by the Master device which
generates the serial clock and all START and STOP
conditions for bus access. The CAT24FC17 operates as
a Slave device. Both the Master and Slave devices can
operate as either transmitter or receiver, but the Master
device controls which mode is activated.
PIN DESCRIPTIONS
SCL: Serial Clock
The CAT24FC17 serial clock input pin is used to clock all
data transfers into or out of the device. This is an input
pin.
SDA: Serial Data/Address
The CAT24FC17 bidirectional serial data/address pin is
used to transfer data into and out of the device. The SDA
pin is an open drain output and can be wire-ORed with
other open drain or open collector outputs.
WP: Write Protect
This input, when tied to GND, allows write operations to
the entire memory. When this pin is tied to V_CC, the
upper half of the memory array is write protected. When
left floating or tied to V_SS, normal read/write operations
are allowed.
Figure 1. Bus Timing ^tF
SCL
tSU:STA
SDA IN
SDA OUT
tHIGH
tR
tLOW
tLOW
tHD:DAT
tHD:STA
tSU:DAT
tAA
tDH
tSU:STO
tBUF
Figure 2. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
Figure 3. Start/Stop Timing
SDA
SCL
Doc. No. 1077, Rev. F
START BIT
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
STOP BIT
4
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice