CAT1024 Datasheet, PDF (6/20 Pages) Catalyst Semiconductor – Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM and Manual Reset

CAT1024, CAT1025
RESET CIRCUIT AC CHARACTERISTICS
Symbol
Parameter
Test
Conditions
Min
Typ
Max
t_PURST
Reset Timeout
Note 2
130
200
270
t_RPD
V_TH to RESET Output Delay
Note 3
5
t_GLITCH
V_CC Glitch Reject Pulse Width
Note 4, 5
30
MR Glitch Manual Reset Glitch Immunity
Note 1
100
t_MRW
MR Pulse Width
Note 1
5
t_MRD
MR Input to RESET Output Delay Note 1
1
Units
ms
µs
ns
ns
µs
µs
POWER-UP TIMING^5,6
Symbol
Parameter
Test
Conditions
Min
Typ
Max
t_PUR
Power-Up to Read Operation
270
t_PUW
Power-Up to Write Operation
270
Units
ms
ms
AC TEST CONDITIONS
Parameter
Input Pulse Voltages
Input Rise and Fall Times
Input Reference Voltages
Output Reference Voltages
Output Load
Test Conditions
0.2V to 0.8V
CC
CC
10 ns
0.3V , 0.7V
CC
CC
0.5V
CC
Current Source: I = 3mA;
OL
C_L = 100pF
RELIABILITY CHARACTERISTICS
Symbol
NEND(5)
TDR(5)
VZAP(5)
ILTH(5)(7)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-Up
Reference Test Method
Min
MIL-STD-883, Test Method 1033 1,000,000
MIL-STD-883, Test Method 1008 100
MIL-STD-883, Test Method 3015 2000
JEDEC Standard 17
100
Max
Units
Cycles/Byte
Years
Volts
mA
Notes:
1. Test Conditions according to “AC Test Conditions” table.
2. Power-up, Input Reference Voltage V_CC = V_TH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
3. Power-Down, Input Reference Voltage V_CC = V_TH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
4. V_CC Glitch Reference Voltage = V_THmin; Based on characterization data
5. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
6. t_PUR and t_PUW are the delays required from the time V_CC is stable until the specified memory operation can be initiated.
7. Latch-up protection is provided for stresses up to 100mA on input and output pins from -1V to V_CC + 1V.
Doc. No. 3008, Rev. M
6