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CAT1024 Datasheet, PDF (1/20 Pages) Catalyst Semiconductor – Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM and Manual Reset
Preliminary Information
CAT1024, CAT1025
ALOGEN FR
Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM and Manual Reset
FEATURES
LEA D F REETM
■ 16-Byte page write buffer
■ Precision power supply voltage monitor
■ Built-in inadvertent write protection
— 5V, 3.3V and 3V systems
— WP pin (CAT1025)
— Five threshold voltage options
■ 1,000,000 Program/Erase cycles
■ Active high or low reset
■ Manual reset input
— Valid reset guaranteed at VCC = 1V
■ 100 year data retention
■ 400kHz I2C bus
■ 8-pin DIP, SOIC, TSSOP, MSOP &
■ 3.0V to 5.5V operation
TDFN (3x3mm foot print) packages
■ Low power CMOS technology
■ Industrial and extended temperature ranges
DESCRIPTION
The CAT1024 and CAT1025 are complete memory and
supervisory solutions for microcontroller-based systems.
A 2k-bit serial EEPROM memory and a system power
supervisor with brown-out protection are integrated
together in low power CMOS technology. Memory
interface is via a 400kHz I2C bus.
The CAT1025 provides a precision VCC sense circuit
and two open drain outputs: one (RESET) drives high
and the other (RESET) drives low whenever VCC falls
below the reset threshold voltage. The CAT1025 also
has a Write Protect input (WP). Write operations are
disabled if WP is connected to a logic high.
The CAT1024 also provides a precision VCC sense
circuit, but has only a RESET output and does not have
a Write Protect input.
The power supply monitor and reset circuit protect
memory and system controllers during power up/down
and against brownout conditions. Five reset threshold
voltages support 5V, 3.3V and 3V systems. If power supply
voltages are out of tolerance reset signals become active,
preventing the system microcontroller, ASIC or peripherals
from operating. Reset signals become inactive typically 200
ms after the supply voltage exceeds the reset threshold
level. With both active high and low reset signals, interface
to microcontrollers and other ICs is simple. In addition, the
RESET pin or a separate input, MR, can be used as an input
for push-button manual reset capability.
The CAT1024/25 memory features a 16-byte page. In
addition, hardware data protection is provided by a VCC
sense circuit that prevents writes to memory whenever VCC
falls below the reset threshold or until VCC reaches the reset
threshold during power up.
Available packages include an 8-pin DIP, 8-pin SOIC, 8-pin
TSSOP, 8-pin TDFN and 8-pin MSOP. The TDFN package
thickness is 0.8mm maximum. TDFN footprint is 3x3mm.
PIN CONFIGURATION
DIP Package (P, L)
SOIC Package (J, W)
TSSOP Package (U, Y)
MSOP Package (R, Z)
MR 1
RESET 2
NC 3
VSS 4
8 VCC
CAT1024 7 NC
6 SCL
5 SDA
(Bottom View)
TDFN Package: 3mm x 3mm
0.8mm maximum height - (RD4, ZD4)
VCC 8
NC 7
SCL 6
SDA 5
CAT1024
1 MR
2 RESET
3 NC
4 VSS
MR 1
RESET 2
RESET 3
VSS 4
CAT1025
8 VCC
7 WP
6 SCL
5 SDA
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
VCC 8
WP 7
SCL 6
SDA 5
CAT1025
1 MR
2 RESET
3 RESET
4 VSS
Doc No. 3008, Rev. M