CAT5419 Datasheet, PDF(5/18 Page) Catalyst Semiconductor – Dual Digitally Programmable Potentiometers (DPP) with 64 Taps and 2-wire Interface

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CAT5419 Datasheet, PDF (5/18 Pages) Catalyst Semiconductor – Dual Digitally Programmable Potentiometers (DPP) with 64 Taps and 2-wire Interface

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CAT5419

WRITE CYCLE LIMITS

Over recommended operating conditions unless otherwise stated.

Symbol Parameter

tWR

Write Cycle Time

Min

Typ Max Units

The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle,

the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.

RELIABILITY CHARACTERISTICS

Over recommended operating conditions unless otherwise stated.

Symbol Parameter

Reference Test Method

Min

Typ

NEND(1) Endurance

MIL-STD-883, Test Method 1033 1,000,000

TDR(1)

Data Retention

MIL-STD-883, Test Method 1008

100

VZAP(1) ESD Susceptibility MIL-STD-883, Test Method 3015

2000

ILTH(1)(2) Latch-Up

JEDEC Standard 17

100

Note:

(1) This parameter is tested initially and after a design or process change that affects the parameter.

(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.

Max Units

Cycles/Byte

Years

Volts

Figure 1. Bus Timing

SCL

tSU:STA

SDA IN

SDA OUT

tHIGH

tLOW

tHD:DAT

tHD:STA

tSU:DAT

tAA

tDH

tSU:STO

tBUF

Figure 2. Write Cycle Timing

SCL

SDA

8TH BIT

BYTE n

ACK

Figure 3. Start/Stop Timing

SDA

SCL

START BIT

tWR

STOP

CONDITION

START

CONDITION

ADDRESS

STOP BIT

Document No. 2115, Rev. F

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