CAT5419 Datasheet, PDF (1/18 Pages) Catalyst Semiconductor – Dual Digitally Programmable Potentiometers (DPP) with 64 Taps and 2-wire Interface

CAT5419
Dual Digitally Programmable Potentiometers (DPP™) with
64 Taps and 2-wire Interface
FEATURES
ALOGEN ^FR
LEA _{D F REETM}
s Two linear-taper digital potentiometers
s 64 resistor taps per potentiometer
s End-to-end resistance 2.5kΩ, 10kΩ, 50kΩ or 100kΩ
s Potentiometer control and memory access via
2-wire interface (I²C like)
s Low wiper resistance, typically 80Ω
s Four non-volatile wiper settings for each
potentiometer
s Recall of wiper settings at power up
s 2.5 to 6.0 volt operation
s Standby current less than 1µA
s 1,000,000 nonvolatile WRITE cycles
s 100 year nonvolatile memory data retention
s 24-lead SOIC, 24-lead TSSOP and BGA
s Write protection for data register
DESCRIPTION
The CAT5419 is two Digitally Programmable
Potentiometers (DPP™) integrated with control logic
and 16 bytes of NVRAM memory.
A separate 6-bit control register (WCR) independently
controls the wiper tap position for each DPP. Associated
with each wiper control register are four 6-bit non-
volatile memory data registers (DR) used for storing up
to four wiper settings. Writing to the wiper control register
or any of the non-volatile data registers is via a 2-wire
serial bus (I²C-like). On power-up, the contents of the
first data register (DR0) for each of the two potentiometers
is automatically loaded into its respective wiper control
registers (WCR).
The Write Protection (WP) pin protects against
inadvertent programming of the data register.
The CAT5419 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications.
PIN CONFIGURATION
SOIC Package (J, W)
TSSOP Package (U, Y)
VCC
RL0
RH0
RW0
A2
WP
SDA
A1
RL1
RH1
RW1
GND
1
24
2
23
3
22
4
21
5
20
6 _CAT 19
7 ⁵⁴¹⁹ 18
8
17
9
16
10
15
11
14
12
13
NC
NC
NC
NC
A0
NC
A3
SCL
NC
NC
NC
NC
SDA
A1
RL1
RH1
RW1
GND
NC
NC
NC
NC
SCL
A3
1
24
2
23
3
22
4
21
5
20
6 _CAT 19
7 ⁵⁴¹⁹ 18
8
17
9
16
10
15
11
14
12
13
WP
A2
RW0
RH0
RL0
VCC
NC
NC
NC
NC
A0
NC
FUNCTIONAL DIAGRAM
RH0 RH1
SCL
SDA
2-WIRE BUS
INTERFACE
WIPER
CONTROL
REGISTERS
WP
A0
A1
CONTROL
A2
LOGIC
A3
NONVOLATILE
DATA
REGISTERS
R _W0
R _W1
A
B
BGA C
D
E
F
1
RW0
RL0
VCC
NC
NC
NC
2
A2
WP
RH0
NC
NC
A0
3
A1
SDA
RH1
NC
A3
SCL
4
RL1
RW1
VSS
NC
NC
NC
Top View - Bump Side Down
RL0 RL1
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Document No. 2115, Rev. F