CAT28LV65 Datasheet, PDF (5/10 Pages) Catalyst Semiconductor – 64K-Bit CMOS PARALLEL E2PROM

Preliminary
Figure 1. A.C. Testing Input/Output Waveform⁽⁴⁾
V_CC - 0.3 V
0.0 V
INPUT PULSE LEVELS
2.0 V
0.6 V
REFERENCE POINTS
Figure 2. A.C. Testing Load Circuit (example)
Vcc
DEVICE
UNDER
TEST
1. 3K
1.8 K
OUTPUT
CL= 100 pF
CAT28LV65
28LV65 F05
CL INCLUDES JIG CAPACITANCE
A.C. CHARACTERISTICS, Write Cycle
V_cc = 3.0V to 3.6V, unless otherwise specified.
28LV65 F07
Symbol
t_WC
t_AS
t_AH
t_CS
t_CH
t_CW(2)
t_OES
t_OEH
t_WP(2)
t_DS
t_DH
t_INIT(1)
t_BLC(1)(3)
t_RB
Parameter
Write Cycle Time
Address Setup Time
Address Hold Time
CE Setup Time
CE Hold Time
CE Pulse Time
OE Setup Time
OE Hold Time
WE Pulse Width
Data Setup Time
Data Hold Time
Write Inhibit Period After Power-up
Byte Load Cycle Time
WE Low to RDY/BSY Low
28LV65-25
Min. Max.
5
0
100
0
0
150
10
10
150
100
0
5
10
0.1 100
220
28LV65-30
Min. Max.
5
0
100
0
0
150
10
10
150
100
0
5
10
0.1 100
220
28LV65-35
Min. Max.
5
0
100
0
0
150
10
10
150
100
0
5
10
0.1 100
220
Units
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
µs
ns
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) A write pulse of less than 20ns duration will not initiate a write cycle.
(3) A timer of duration t_BLC max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin;
however a transition from HIGH to LOW within t_BLC max. stops the timer.
(4) Input rise and fall times (10% and 90%) < 10 ns.
5
Doc. No. 25041-00 2/98