CAT28LV65 Datasheet, PDF (1/10 Pages) Catalyst Semiconductor – 64K-Bit CMOS PARALLEL E2PROM

Preliminary
CAT28LV65
64K-Bit CMOS PARALLEL E²PROM
FEATURES
s 3.0V to 3.6V Supply
s Read Access Times:
– 250/300/350ns
s Low Power CMOS Dissipation:
– Active: 8 mA Max.
– Standby: 100 µA Max.
s Simple Write Operation:
– On-Chip Address and Data Latches
– Self-Timed Write Cycle with Auto-Clear
s Fast Write Cycle Time:
– 5ms Max.
s Commercial, Industrial and Automotive
Temperature Ranges
DESCRIPTION
The CAT28LV65 is a low voltage, low power, CMOS
parallel E²PROM organized as 8K x 8-bits. It requires a
simple interface for in-system programming. On-chip
address and data latches, self-timed write cycle with
auto-clear and V_CC power up/down write protection
eliminate additional timing and protection hardware.
DATA Polling, RDY/BUSY and Toggle status bit signal
the start and end of the self-timed write cycle. Addition-
ally, the CAT28LV65 features hardware and software
write protection.
s CMOS and TTL Compatible I/O
s Automatic Page Write Operation:
– 1 to 32 Bytes in 5ms
– Page Load Timer
s End of Write Detection:
– Toggle Bit
– DATA Polling
– RDY/BUSY
s Hardware and Software Write Protection
s 100,000 Program/Erase Cycles
s 100 Year Data Retention
The CAT28LV65 is manufactured using Catalyst’s ad-
vanced CMOS floating gate technology. It is designed to
endure 100,000 program/erase cycles and has a data
retention of 100 years. The device is available in JEDEC
approved 28-pin DIP, 28-pin TSOP, 28-pin SOIC or 32-
pin PLCC packages.
BLOCK DIAGRAM
A5–A12
VCC
CE
OE
WE
A0–A4
RDY/BUSY
ADDR. BUFFER
& LATCHES
INADVERTENT
WRITE
PROTECTION
CONTROL
LOGIC
TIMER
ADDR. BUFFER
& LATCHES
ROW
DECODER
HIGH VOLTAGE
GENERATOR
DATA POLLING,
RDY/BUSY &
TOGGLE BIT
COLUMN
DECODER
8,192 x 8
E²PROM
ARRAY
32 BYTE PAGE
REGISTER
I/O BUFFERS
I/O0–I/O7
28LV65 F01
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 25041-00 2/98