CAT28LV256 Datasheet, PDF (5/10 Pages) Catalyst Semiconductor – 256K-Bit CMOS PARALLEL E2PROM

Figure 1. A.C. Testing Input/Output Waveform⁽²⁾
VCC - 0.3V
0.0 V
INPUT PULSE LEVELS
2.0 V
0.6 V
REFERENCE POINTS
Figure 2. A.C. Testing Load Circuit (example)
V_cc
CAT28LV256
28LV256 F04
DEVICE
UNDER
TEST
1.8K
OUTPUT
1.3K
CL = 100 pF
CL INCLUDES JIG CAPACITANCE
28LV256 F05
A.C. CHARACTERISTICS, Write Cycle
V_CC = 3.0V to 3.6V, unless otherwise specified
Symbol
tWC
tAS
tAH
tCS
tCH
tCW(3)
tOES
tOEH
tWP(3)
tDS
tDH
tINIT(1)
tBLC(1)(4)
Parameter
Write Cycle Time
Address Setup Time
Address Hold Time
CE Setup Time
CE Hold Time
CE Pulse Time
OE Setup Time
OE Hold Time
WE Pulse Width
Data Setup Time
Data Hold Time
Write Inhibit Period After Power-up
Byte Load Cycle Time
28LV256-20 28LV256-25 28LV256-30
Min. Max. Min. Max. Min. Max. Units
10
10
10 ms
0
0
0
ns
100
100
100
ns
0
0
0
ns
0
0
0
ns
150
150
150
ns
0
0
0
ns
0
0
0
ns
150
150
150
ns
50
50
50
ns
0
0
0
ns
5
10 5
10 5 10 ms
0.15 100 0.15 100 0.15 100 µs
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Input rise and fall times (10% and 90%) < 10 ns.
(3) A write pulse of less than 20ns duration will not initiate a write cycle.
(4) A timer of duration t_BLC max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin;
however a transition from HIGH to LOW within t_BLC max. stops the timer.
5
Doc. No. 25040-00 4/01 P-1